Quectel SC66 Hardware Design page 38

CSI0_LN0_P 79 AI
CSI0_LN1_N 82 AI
CSI0_LN1_P 81 AI
CSI0_LN2_N 84 AI
CSI0_LN2_P 83 AI
CSI0_LN3_N 86 AI
CSI0_LN3_P 85 AI
MCAM_MCLK 99 DO
SCAM_MCLK 100 DO
MCAM_RST 74 DO
MCAM_PWDN 73 DO
SCAM_RST 72 DO
SCAM_PWDN 71 DO
CAM_I2C_SCL
75 OD
0
CAM_I2C_SDA
76 OD
0
DCAM_MCLK 194 DO
DCAM_RST 180 DO
SC66_Hardware_Design
of front camera (-)
MIPI lane 0 data signal
of front camera (+)
MIPI lane 1 data signal
of front camera (-)
MIPI lane 1 data signal
of front camera (+)
MIPI lane 2 data signal
of front camera (-)
MIPI lane 2 data signal
of front camera (+)
MIPI lane 3 data signal
of front camera (-)
MIPI lane 3 data signal
of front camera (+)
Master clock signal of
rear camera
Master clock signal of
front camera
Reset signal of rear
camera
V max=0.45V
OL
V min=1.35V
Power down signal of
OH
rear camera
Reset signal of front
camera
Power down signal of
front camera
I2C clock signal of
camera
I2C data signal of
camera
Master clock signal of
V max=0.45V
depth camera
OL
V min=1.35V
OH
Reset signal of depth
Smart LTE Module Series
SC66 Hardware Design
impedance.
85Ω differential
impedance.
85Ω differential
impedance.
85Ω differential
impedance.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
37 / 139