Quectel SC66 Hardware Design page 77

GPIO_04B 14
CSI0_CLK_N 78
CSI0_CLK_P 77
CSI0_LN0_N 80
CSI0_LN0_P 79
CSI0_LN1_N 82
CSI0_LN1_P 81
CSI0_LN2_N 84
CSI0_LN2_P 83
CSI0_LN3_N 86
CSI0_LN3_P 85
CSI1_CLK_N 89
CSI1_CLK_P 88
CSI1_LN0_N 91
CSI1_LN0_P 90
CSI1_LN1_N 93
CSI1_LN1_P 92
CSI1_LN2_N 95
CSI1_LN2_P 94
CSI1_LN3_N 97
CSI1_LN3_P 96
CSI2_CLK_N 184
CSI2_CLK_P 183
SC66_Hardware_Design
Camera AVDD power
DO
LDO enable pin
AI MIPI clock signal of front camera (-)
AI MIPI clock signal of front camera (+)
MIPI lane 0 data signal of front camera
AI
(-)
MIPI lane 0 data signal of front camera
AI
(+)
MIPI lane 1 data signal of front camera
AI
(-)
MIPI lane 1 data signal of front camera
AI
(+)
MIPI lane 2 data signal of front camera
AI
(-)
MIPI lane 2 data signal of front camera
AI
(+)
MIPI lane 3 data signal of front camera
AI
(-)
MIPI lane 3 data signal of front camera
AI
(+)
AI MIPI clock signal of rear camera (-)
AI MIPI clock signal of rear camera (+)
AI MIPI data0 signal of rear camera (-)
AI MIPI data0 signal of rear camera (+)
AI MIPI data 1 signal of rear camera (-)
AI MIPI data 1 signal of rear camera (+)
AI MIPI data 2 signal of rear camera (-)
AI MIPI data 2 signal of rear camera (+)
AI MIPI data 3 signal of rear camera (-)
AI MIPI data 3 signal of rear camera (+)
AI MIPI clock signal of depth camera (-)
AI MIPI clock signal of depth camera (+)
Smart LTE Module Series
SC66 Hardware Design
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