Quectel SC66 Hardware Design page 36

DSI1_LN3_P 110
Camera Interfaces
Pin
Pin Name I/O
No.
CSI1_CLK_N 89 AI
CSI1_CLK_P 88 AI
CSI1_LN0_N 91 AI
CSI1_LN0_P 90 AI
CSI1_LN1_N 93 AI
CSI1_LN1_P 92 AI
CSI1_LN2_N 95 AI
CSI1_LN2_P 94 AI
CSI1_LN3_N 97 AI
CSI1_LN3_P 96 AI
CSI2_CLK_N 184 AI
SC66_Hardware_Design
signal (-)
LCD1 MIPI lane 3 data
signal (+)
DC
Description
Characteristics
MIPI clock signal of
rear camera (-)
MIPI clock signal of
rear camera (+)
MIPI lane 0 data signal
of rear camera (-)
MIPI lane 0 data signal
of rear camera (+)
MIPI lane 1 data signal
of rear camera (-)
MIPI lane 1 data signal
of rear camera (+)
MIPI lane 2 data signal
of rear camera (-)
MIPI lane 2 data signal
of rear camera (+)
MIPI lane 3 data signal
of rear camera (-)
MIPI lane 3 data signal
of rear camera (+)
MIPI clock signal of
depth camera (-)
Smart LTE Module Series
SC66 Hardware Design
impedance.
Comment
85Ω differential
impedance.
85Ω differential
impedance.
85Ω differential
impedance.
85Ω differential
impedance.
85Ω differential
impedance.
85Ω differential
impedance.
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