Quectel SC66 Hardware Design page 71

DSI0_LN2_P 121
DSI0_LN3_N 124
DSI0_LN3_P 123
DSI1_CLK_N 103
DSI1_CLK_P 102
DSI1_LN0_N 105
DSI1_LN0_P 104
DSI1_LN1_N 107
DSI1_LN1_P 106
DSI1_LN2_N 109
DSI1_LN2_P 108
DSI1_LN3_N 111
DSI1_LN3_P 110
LCD1_RST 113
SC66_Hardware_Design
signal (-)
LCD0 MIPI lane 2 data
AO
signal (+)
LCD0 MIPI lane 3 data
AO
signal (-)
LCD0 MIPI lane 3 data
AO
signal (+)
AO LCD1 MIPI clock signal (-)
LCD1 MIPI clock signal
AO
(+)
LCD1 MIPI lane 0 data
AO
signal (-)
LCD1 MIPI lane 0 data
AO
signal (+)
LCD1 MIPI lane 1 data
AO
signal (-)
LCD1 MIPI lane 1 data
AO
signal (+)
LCD1 MIPI lane 2 data
AO
signal (-)
LCD1 MIPI lane 2 data
AO
signal (+)
LCD1 MIPI lane 3 data
AO
signal (-)
LCD1 MIPI lane 3 data
AO
signal (+)
DO LCD1 reset signal
Smart LTE Module Series
SC66 Hardware Design
V max=0.45V
OL
V min=1.35V
OH
1.8V power domain.
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