Quectel SC66 Hardware Design page 34

Lte module
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TP0_RST
138
DO
TP0_INT
139
DI
TP0_I2C_SCL
140
OD
TP0_I2C_SDA
206
OD
TP1_RST
136
DO
TP1_INT
137
DI
TP1_I2C_SCL
205
OD
TP1_I2C_SDA
204
OD
LCM Interfaces
Pin
Pin Name
I/O
No.
PWM
152
DO
LCD0_RST
127
DO
LCD0_TE
126
DI
DSI0_CLK_N
116
AO
DSI0_CLK_P
115
AO
DSI0_LN0_N
118
AO
DSI0_LN0_P
117
AO
DSI0_LN1_N
120
AO
SC66_Hardware_Design
Reset signal of
V
max=0.45V
OL
touch panel (TP0)
V
min=1.35V
OH
Interrupt signal of
V
max=0.63V
IL
touch panel (TP0)
V
min=1.17V
IH
I2C clock signal of
touch panel (TP0)
I2C data signal of
touch panel (TP0)
Reset signal of
V
max=0.45V
OL
touch panel (TP1)
V
min=1.35V
OH
Interrupt signal of
V
max=0.63V
IL
touch panel (TP1)
V
min=1.17V
IH
I2C clock signal of
touch panel (TP1)
I2C data signal of
touch panel (TP1)
Description
DC Characteristics
The voltage is equal
PWM signal output
to VBAT voltage.
V
max=0.45V
OL
LCD0 reset signal
V
min=1.35V
OH
LCD0 tearing effect
V
max=0.63V
IL
signal
V
min=1.17V
IH
LCD0 MIPI clock
signal (-)
LCD0 MIPI clock signal
(+)
LCD0 MIPI lane 0 data
signal (-)
LCD0 MIPI lane 0 data
signal (+)
LCD0 MIPI lane 1 data
signal (-)
Smart LTE Module Series
SC66 Hardware Design
1.8V power domain.
Comment
Cannot be multiplexed
into a general-purpose
GPIO.
1.8V power domain;
It should not be pulled
up.
1.8V power domain.
85Ω differential
impedance.
85Ω differential
impedance.
85Ω differential
impedance.
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