Quectel SC66 Hardware Design page 37

CSI2_CLK_P 183 AI
CSI2_LN0_N 186 AI
CSI2_LN0_P 185 AI
CSI2_LN1_N 188 AI
CSI2_LN1_P 187 AI
CSI2_LN2_N 190 AI
CSI2_LN2_P 189 AI
CSI2_LN3_N 192 AI
CSI2_LN3_P 191 AI
CSI0_CLK_N 78 AI
CSI0_CLK_P 77 AI
CSI0_LN0_N 80 AI
SC66_Hardware_Design
MIPI clock signal of
depth camera (+)
MIPI lane 0 data signal
of depth camera (-)
MIPI lane 0 data signal
of depth camera (+)
MIPI lane 1 data signal
of depth camera (-)
MIPI lane 1 data signal
of depth camera (+)
MIPI lane 2 data signal
of depth camera (-)
MIPI lane 2 data signal
of depth camera (+)
MIPI lane 3 data signal
of depth camera (-)
MIPI lane 3 data signal
of depth camera (+)
MIPI clock signal of
front camera (-)
MIPI clock signal of
front camera (+)
MIPI lane 0 data signal
Smart LTE Module Series
SC66 Hardware Design
85Ω differential
impedance.
85Ω differential
impedance.
85Ω differential
impedance.
Can be multiplexed
into differential data of
the fourth camera (-).
85Ω differential
impedance.
Can be multiplexed
into differential data of
the fourth camera (+).
85Ω differential
impedance.
Can be multiplexed
into differential clock of
the fourth camera (-).
85Ω differential
impedance.
Can be multiplexed
into differential clock of
the fourth camera (+).
85Ω differential
impedance.
85Ω differential
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