Reference Circuit Design For Microphone Interface - Quectel SC66 Hardware Design

EAR_P 53 AO
EAR_M 52 AO
SPK_P 55 AO
SPK_M 54 AO
HPH_R 51 AO
HPH_REF 50 AI
HPH_L 49 AO
HS_DET 48 AI

The module offers three audio input channels, including one differential input pair and two
single-ended channels. The three sets of MICs are integrated with internal bias voltage.

The output voltage range of MIC_BIAS is programmable between 1.6V and 2.9V, and the maximum
output current is 3mA.

The earpiece interface uses differential output.

The loudspeaker interface uses differential output as well. The output channel is available with a
Class-D amplifier whose maximum output power is 1.5W when the load is 8Ω.

The headphone interface features stereo left and right channel output, and headphone insertion
detection function is supported.

3.22.1. Reference Circuit Design for Microphone Interface

MIC1_P
MIC1_N
Module
Figure 30: Reference Circuit Design for Analog ECM-type Microphone
SC66_Hardware_Design
Earpiece output (+)
Earpiece output (-)
Speaker output (+)
Speaker output (-)
Headphone right channel output
Headphone reference ground
Headphone left channel output
Headset insertion detection
R1
0R
R2
0R
33pF
Smart LTE Module Series
SC66 Hardware Design
It should be connected
to main GND
High level by default.
D1
ECM-
Type
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