Quectel SC66 Hardware Design page 35

DSI0_LN1_P 119 AO
DSI0_LN2_N 122 AO
DSI0_LN2_P 121 AO
DSI0_LN3_N 124 AO
DSI0_LN3_P 123 AO
LCD1_RST 113 DO
DSI1_CLK_N 103
DSI1_CLK_P 102
DSI1_LN0_N 105
DSI1_LN0_P 104
DSI1_LN1_N 107
DSI1_LN1_P 106
DSI1_LN2_N 109
DSI1_LN2_P 108
DSI1_LN3_N 111
SC66_Hardware_Design
LCD0 MIPI lane 1 data
signal (+)
LCD0 MIPI lane 2 data
signal (-)
LCD0 MIPI lane 2 data
signal (+)
LCD0 MIPI lane 3 data
signal (-)
LCD0 MIPI lane 3 data
signal (+)
V max=0.45V
OL
LCD1 reset signal
V min=1.35V
OH
LCD1 MIPI clock signal
(-)
LCD1 MIPI clock signal
(+)
LCD1 MIPI lane 0 data
signal (-)
LCD1 MIPI lane 0 data
signal (+)
LCD1 MIPI lane 1 data
signal (-)
LCD1 MIPI lane 1 data
signal (+)
LCD1 MIPI lane 2 data
signal (-)
LCD1 MIPI lane 2 data
signal (+)
LCD1 MIPI lane 3 data
Smart LTE Module Series
SC66 Hardware Design
85Ω differential
impedance.
85Ω differential
impedance.
1.8V power domain.
85Ω differential
impedance.
85Ω differential
impedance.
85Ω differential
impedance.
85Ω differential
impedance.
85Ω differential
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