ARM DSTREAM-ST System And Interface Design Reference Manual
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ARM DSTREAM-ST System And Interface Design Reference Manual

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ARM
DSTREAM-ST
®
Version 1.0
System and Interface Design Reference Guide
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
ARM 100893_0100_00_en

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  • Page 1 DSTREAM-ST ® Version 1.0 System and Interface Design Reference Guide Copyright © 2017 ARM Limited or its affiliates. All rights reserved. ARM 100893_0100_00_en...
  • Page 2 Use of the word “partner” in reference to ARM’s customers is not intended to create or refer to any partnership relationship with any other company.
  • Page 3 It is recommended that ESD precautions be taken when handling DSTREAM-ST equipment. The DSTREAM-ST modules generate, use, and can radiate radio frequency energy and may cause harmful interference to radio communications. There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful...

  • Page 4: Table Of Contents

    Voltage domains of the DSTREAM-ST unit ............2-36 Series termination ....................2-37 Chapter 3 DSTREAM-ST USER Input/Output (IO) connections ® About the USER I/O connector pinouts ..............3-39 ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 5 PCB track impedance ....................4-43 Signal requirements ....................4-44 Modeling ........................4-45 Chapter 5 Reference About adaptive clocking to synchronize the JTAG port .......... 5-47 ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 6 Figure 2-15 Reset output .......................... 2-34 Figure 2-16 Reset output with feedback ....................2-34 Figure 2-17 VTRef input ..........................2-35 Figure 2-18 VTRef input (decoupled) ......................2-35 ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 7 Timing diagram for the Basic JTAG synchronizer ..............5-48 Figure 5-3 JTAG port synchronizer for single rising-edge D-type ASIC design rules ......5-48 Figure 5-4 Timing diagram for the D-type JTAG synchronizer ..............5-49 ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 8 DSTREAM-ST JTAG Characteristics ..................2-29 Table 2-8 Typical series terminating resistor values ................2-37 Table 3-1 USER I/O pin connections ..................... 3-39 Table 4-1 Data setup and hold ......................4-44 ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. Non-Confidential...

  • Page 9: Preface

    Preface This preface introduces the ARM DSTREAM-ST System and Interface Design Reference Guide. ® It contains the following: • About this book on page ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. Non-Confidential...

  • Page 10: About This Book

    Lists other information that might be useful when working with DSTREAM-ST. Glossary The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.
  • Page 11 A concise explanation of your comments. ARM also welcomes general suggestions for additions and improvements. Note ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. Other information •...
  • Page 12 DSTREAM-ST debug and trace unit enables powerful software debug and optimization on ® an ARM processor-based hardware target. Use the information in this chapter to design your own ARM- architecture-based devices and Printed Circuit Boards (PCBs) that can be debugged using the DSTREAM-ST unit.

  • Page 13: Reset Signals

    LOW by the debugger to re-initialize the target system. Note It is expected that the assertion of the nSRST line by the DSTREAM-ST unit will cause a warm reset of the target system. If the nSRST line triggers a power-on reset (POR), then the debug connection might be lost.

  • Page 14: Figure 1-1 Example Reset Circuit Logic

    TAP RESET TRST Open-drain reset devices e.g. STM1001 Processor SYSTEM RESET RESET nSRST 100R 100nF Manual reset To other logic Figure 1-1 Example reset circuit logic ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 1-14 Non-Confidential...

  • Page 15: Working With Application-Specific Integrated Circuits (Asic) Or System-On-Chips (Soc)

    If your system contains multiple devices that each have a JTAG Test Access Port (TAP) controller, you must serially chain them so that DSTREAM-ST can communicate with all of them simultaneously. The chaining can either be within the ASIC, or externally.
  • Page 16 You can use this to break the internal daisy chaining of TDO and TDI signals, and to multiplex out independent JTAG ports on pins that are used for another purpose during normal operation. ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 1-16 Non-Confidential...

  • Page 17: Physical And Electrical Connection Guidelines

    50Ω. Target interface logic levels DSTREAM-ST is designed to interface with a wide range of target system logic levels. It does this by adapting its output drive and input threshold to a reference voltage supplied by the target system.

  • Page 18: Figure 1-4 Target Interface Logic Levels

    DSTREAM-ST can adapt interface levels down to VTRef of 1.2V. By default, the nTRST and nSRST signals are pulled-up by 4.7K resistors within DSTREAM-ST and driven (strong) low during resets. This allows the reset signals to be driven by other open-drain devices or switches on the target board.

  • Page 19: Arm

    Chapter 2 DSTREAM-ST target interface connections ® This chapter describes the target connector pinouts and their interface signals available on the ARM DSTREAM-ST unit. It contains the following sections: • 2.1 About the ARM JTAG 20 connector pinouts and interface signals on page 2-20.

  • Page 20: About The Arm Jtag 20 Connector Pinouts And Interface Signals

    JTAG 20 connector pinouts and interface signals ® The ARM JTAG 20 connector is a 20-way 2.54mm pitch connector. You can use it in either standard JTAG (IEEE 1149.1) mode or Serial Wire Debug (SWD) mode. The following figure shows the ARM JTAG 20 connector pinout:...
  • Page 21 Input/ The System Reset pin fully resets the target. This signal can be initiated by DSTREAM-ST or by the Output target board (which is then detected by DSTREAM-ST). nSRST is typically pulled HIGH on the target and pulled strong-LOW to initiate a reset.

  • Page 22: About The Coresight ™ 20 Connector Pinouts And Interface Signals

    Table 2-3 CoreSight 20 interface pinout table Signal name Signal name diagram diagram VTRef TMS/SWDIO TCK/SWCLK TDO/SWO KEY (NC) nSRST RTCK/TRACECLK SWO/TraceD0 nTRST/TraceD1 DBGRQ/TraceD2 DBGACK /TraceD3 ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 2-22 Non-Confidential...

  • Page 23: Table 2-4 Coresight 20 Signals

    RTCK Input The Return Test Clock pin echoes the test clock signal back to DSTREAM-ST for use with adaptive mode clocking. If RTCK is generated by the target processor, you are advised to series terminate it. RTCK can be pulled HIGH or LOW on the target when not in use.
  • Page 24 Description VTRef Input The Voltage Target Reference pin supplies DSTREAM-ST with the debug rail voltage of the target to match its I/O logic levels. VTRef can be tied HIGH on the target. Note If VTRef is pulled HIGH by a resistor, its value must be no greater than 100Ω.

  • Page 25: About Serial Wire Debug (Swd)

    For clarity, the diagrams shown in the following figure separate the SWDIO line to show when it is driven by either the DSTREAM-ST unit or target: ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 2-25 Non-Confidential...

  • Page 26: Figure 2-4 Swd Timing Diagrams

    Tri-State Figure 2-4 SWD timing diagrams The DSTREAM-ST unit writes data to SWDIO on the falling edge of SWDCLK. The DSTREAM-ST unit reads data from SWDIO on the rising edge of SWDCLK. The target writes data to SWDIO on the rising edge of SWDCLK.

  • Page 27: About Trace Signals

    1.65V. Hot-plugging If you power-up the DSTREAM-ST unit when it is plugged into an unpowered target, or if you plug an unpowered DSTREAM-ST unit into a powered target, trace functionality is not damaged. If you connect an unpowered DSTREAM-ST unit to a powered target, there is a maximum leakage current into the DSTREAM-ST unit of ±10μA on any of the debug or trace signals.

  • Page 28: About Jtag Port Timing Characteristics

    IEEE 1149.1 specification. TMS and TDI are setup by the DSTREAM-ST unit on the falling edge of TCK. This is then sampled by the target on the rising edge of TCK. Ideally, the target device must output TDO signal on the falling edge of TCK for DSTREAM-ST to sample it on the next rising edge of TCK.

  • Page 29: Table 2-7 Dstream-St Jtag Characteristics

    Note There are no separate timing requirements for the adaptive clocking mode. In adaptive mode, the DSTREAM-ST unit samples TDO on the rising edge of RTCK and not TCK, so TDO timing is relative to RTCK. The following table shows the timing requirements for the JTAG signals on the DSTREAM-ST probe:...

  • Page 30: About Jtag Port Buffering

    TDO pin of the target device with the appropriate series termination resistor: JTAG CONNECTOR Processor/ASIC Figure 2-8 JTAG connection with TDO buffer Sometimes, two or more devices are daisy-chained together in the target system: ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 2-30 Non-Confidential...

  • Page 31: Figure 2-9 Daisy-Chained Jtag Connection Without Buffers

    To avoid this issue, buffering should always be used where the TCK signal is split: ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 2-31 Non-Confidential...

  • Page 32: Figure 2-10 Daisy-Chained Jtag Connection With Tck Buffers

    It might be beneficial to use the same type of buffers on the TDI and TMS signals as on the TCK signals, for example: ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 2-32 Non-Confidential...

  • Page 33: Figure 2-11 Jtag Connection With De-Skewed Buffers

    Buffers with a drive strength of 24mA or above are recommended. For guidance on selection of series termination resistors, see 2.9 Series termination on page 2-37. ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 2-33 Non-Confidential...

  • Page 34: I/O Diagrams For The Dstream-St Connectors

    2.7 I/O diagrams for the DSTREAM-ST connectors I/O diagrams for the DSTREAM-ST connectors The diagrams show the pin I/O circuits for the debug and trace connectors on the DSTREAM-ST unit. Diagram A - Input The input circuit diagram is shown in the following figure:...

  • Page 35: Figure 2-17 Vtref Input

    Figure 2-18 VTRef input (decoupled) Diagram H - AC Ground The AC Ground circuit diagram is shown in the following figure: 100nF Figure 2-19 AC Ground ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 2-35 Non-Confidential...

  • Page 36: Voltage Domains Of The Dstream-St Unit

    The DSTREAM-ST unit supports two separate voltage domains to work with debug and trace interfaces on differing voltage rails. When using either the CoreSight 20 or ARM JTAG 20 connector, only one voltage domain is supported and is preset through the VTRef signal from the target.

  • Page 37: Series Termination

    ARM recommends that all outputs from the target system be simulated, and, if necessary, series terminated to ensure that a reliable signal is delivered to the DSTREAM-ST unit. Some overshoot/ undershoot is acceptable but it is recommended to keep this below ~0.5V. Beyond this point, the clamping diodes at the receivers will start to cause high transient currents which in turn cause increased crosstalk, radio emissions and target power usage.
  • Page 38 Chapter 3 DSTREAM-ST USER Input/Output (IO) ® connections This chapter describes the additional input and output connections provided in the ARM DSTREAM-ST unit. It contains the following section: • 3.1 About the USER I/O connector pinouts on page 3-39. ARM 100893_0100_00_en Copyright ©...

  • Page 39: About The User I/O Connector Pinouts

    +3.3V Figure 3-1 USER I/O connector pinouts Warning You must establish a common ground between the DSTREAM-ST unit and the target hardware before you connect any of the USER I/O signals. USER I/O pinouts The table shows the USER I/O pinouts available on DSTREAM-ST.
  • Page 40 This is intended as a voltage reference for external circuitry and is current limited to approximately 50mA. Pin 10 Note USER inputs are not currently supported by the DSTREAM-ST firmware and are reserved for future use. ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
  • Page 41 4.1 Overview of high-speed design on page 4-42. • 4.2 PCB track impedance on page 4-43. • 4.3 Signal requirements on page 4-44. • 4.4 Modeling on page 4-45. ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 4-41 Non-Confidential...

  • Page 42: Target Board Design For Tracing With Arm Dstream-St

    4.1 Overview of high-speed design Overview of high-speed design Failure to observe high-speed design rules when designing a target system containing an ARM Embedded Trace Macrocell (ETM) trace port can result in incorrect trace data being captured. You must give serious consideration to high-speed signals when designing the target system.

  • Page 43: Pcb Track Impedance

    0.005 inch height above ground 0.007 inch width track 0.0014 inch thickness (1 oz. finished weight) 4.5 (FR4 laminate) Note As the track width increases, the impedance decreases. ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 4-43 Non-Confidential...

  • Page 44: Signal Requirements

    0.75ns Data hold low Note DSTREAM-ST supports DDR clocking mode. Data is output on each edge of the TRACECLK signal and TRACECLK (max) <= 300MHz. Switching thresholds The DSTREAM-ST senses the target signaling reference voltage (VTRef) and automatically adjusts its switching thresholds to VTRef/2.

  • Page 45: Modeling

    4.4 Modeling Modeling For trace bit rates of 0-600Mbps, basic signal integrity can be established using simplified modeling. The bulk of the transmission line model consists of the cable used between the DSTREAM-ST unit and the target. • The 30cm CoreSight cable is made using 0.635mm pitch ribbon and can be modeled as a 66Ω...

  • Page 46: Reference

    Chapter 5 Reference Lists other information that might be useful when working with DSTREAM-ST. It contains the following section: • 5.1 About adaptive clocking to synchronize the JTAG port on page 5-47. ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved.

  • Page 47: About Adaptive Clocking To Synchronize The Jtag Port

    A system where scan chains external to the ARM macrocell must meet single rising-edge D-type design rules. When adaptive clocking is enabled, DSTREAM-ST issues a TCK signal and waits for the RTCK signal to come back. DSTREAM-ST does not progress to the next TCK until RTCK is received.

  • Page 48: Figure 5-1 Basic Jtag Port Synchronizer

    Shift En RTCK TAP Ctrl CKEN State nCLR nCLR nCLR Machine nTRST nRESET Figure 5-3 JTAG port synchronizer for single rising-edge D-type ASIC design rules ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 5-48 Non-Confidential...

  • Page 49: Figure 5-4 Timing Diagram For The D-Type Jtag Synchronizer

    RTCK and TDO signals so that they only change state at the edges of TCK. TCKRisingEn TCKFallingEn RTCK TAPC State Figure 5-4 Timing diagram for the D-type JTAG synchronizer ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 5-49 Non-Confidential...

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