Chipset Features Setup - QDI BrillianX 8V Manual

Chipset Features Setup

Figure-5 Chipset Features Setup Menu
The following indicates the options for each item and describes their meaning.
Item
Bank 0/1, 2/3, 4/5
l
DRAM Timing
SDRAM
l
Cycle Length
DRAM Read
l
Pipeline
Cache Rd+CPU wt
l
pipeline
Cache Timing
l
Video BIOS
l
Cacheable
System BIOS
l
Cacheable
Memory Hole At
l
15Mb Addr
Option
60ns These items are of selected EDO DRAM
70ns read/write timing. You must ensure that your
DIMMs are as fast as 60ns, otherwise you have
to select 70ns.
3 Define the CLT timing parameter of SDRAM
expressed in 66MHz clocks,
Latency Time = 2 clocks
Latency Time = 3 clocks
Enabled Enabl e s DRAM Read Pipeline.
Disabled Disables DRAM Read Pipeline.
Enabled Enables Read Around Write.
Disabled Disables Read Around Write.
Fast This item i s used to select Cache Read/Write
Fastest speed, "Fast" is the optimize sel e ction.
Enabled Besides conventional memory, video BIOS area
is also cacheable.
Disabled Video BIOS area is not cacheable.
Enabled Besides conventional memory, the system BIOS
area is also cacheable.
Disabled The system BIOS area is not cacheable.
Enabled Memory Hole at 15-16M i s reserved for expanded
PCI card.
Disabled Do not set thi s memory hole.
M a nua l f or B r i l l i a nX 8V
Chapter 3
Description