Advanced Chipset Features Setup - QDI SynactiX 5EP Manual

Advanced Chipset Features Setup

Figure-5 Advanced Chipset Features Menu
The following indicates the options for each item and describes their meaning.
Item
SDRAM CAS
$
"
Latency Time
SDRAM Cycle Time 5/7
$"
Tras/Trc 6/8
SDRAM RAS-to-CAS 2
$"
Delay 3
SDRAM RAS 2
$
"
Precharge Time 3
System BIOS
$
"
Cacheable
Video BIOS
$
"
Cacheable
Memory hole at
$
"
15M-16M
CPU Latency Timer
$
"
Delayed
$
"
Transaction
$ AGP Graphics
"
Aperture Size
$ AGP Device 4X
"
support
Option
3 Define the CLT timing parameter of SDRAM
2
Set DRAM Tras/Trc Cycle time is 5/7 SCLKs or 6/8
SCLKs.Tras is RAS activing time. Trc is RAS Cycle
time.
Set SDRAM RAS# to CAS# delay 3 SCLKs or 2
SCLKs.
Set SDRAM RAS# Percharge is 3 or 2.
Enabled Besides conventional memory, the system BIOS
Disabled area is also cacheable.
Besides conventional memory, video RAM area
Enabled
is also cacheable.
Disabled Video RAM area is not cacheable.
Enabled Memory hole at 15-16M is reserved for
expanded ISA card.
Disabled Do not set this memory hole.
Enabled Define the CPU Latency Timer
Disabled
Enabled Disabled is normal operation.Enabled for slow
Disabled speed ISA device in system.
64MB Set the effective size of the Graphics Aperture to
32MB be used in the particular GART Configuration.
Enabled Support AGP4X mode
Disabled Not Support AGP4X mode
Manual for SynactiX 5EP/5EI
Chapter 3
Description