Texas Instruments TMS320C6745 Manual page 144

TMS320C6745, TMS320C6747
SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014
Table 6-66. Additional
No.
Max delay for slave to
deassert SPI1_ENA after final
18 t SPI1_CLK edge to ensure
d(SPC_ENA)M
master does not begin the
next transfer.
Delay from final SPI1_CLK
edge to
20 t
d(SPC_SCS)M
master deasserting
SPI1_SCS
Max delay for slave SPI to drive SPI1_ENA valid after
21 t master asserts SPI1_SCS to delay the
d(SCSL_ENAL)M
master from beginning the next transfer,
Delay from SPI1_SCS active
22 t
d(SCS_SPC)M
to first SPI1_CLK
Delay from assertion of
23 t SPI1_ENA low to first
d(ENA_SPC)M
SPI1_CLK edge.
(1) These parameters are in addition to the general timings for SPI master modes
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
144 Peripheral Information and Electrical Specifications
(1)
SPI1 Master Timings, 5-Pin Option
PARAMATER
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
(4)
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
(5) (6)
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
(7) (8) (9)
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
(10)
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
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(2) (3)
MIN
0.5t + P -3
c(SPC)M
P - 3
0.5t + P -3
c(SPC)M
P - 3
2P -5
0.5t + 2P -5
c(SPC)M
2P -5
0.5t + 2P -5
c(SPC)M
0.5t
0.5t
(Table 6-63).
Copyright © 2008–2014, Texas Instruments Incorporated
www.ti.com
MAX UNIT
0.5t +P+5
c(SPC)M
P+5
ns
0.5t +P+5
c(SPC)M
P+5
ns
C2TDELAY + P ns
ns
3P + 3
+ 3P + 3
c(SPC)M
ns
3P + 3
+ 3P + 3
c(SPC)M