Intel M50CYP1UR Series Integration And Service Manual page 105

Intel® Server System M50CYP1UR Family System Integration and Service Guide
Post Upper Nibble
Code
8h 4h 2h
(Hex)
MRC Progress Codes – At this point the MRC Progress Code sequence is executed.
31 0 0 1
32 0 0 1
33 0 0 1
34 0 0 1
35 0 0 1
36 0 0 1
4F 0 1 0
Memory Feature Progress Codes
C1 1 1 0
C2 1 1 0
C3 1 1 0
C4 1 1 0
C5 1 1 0
C6 1 1 0
C7 1 1 0
C9 1 1 0
CA 1 1 0
CB 1 1 0
CC 1 1 0
CD 1 1 0
CE 1 1 0
CF 1 1 0
D0 1 1 0
D1 1 1 0
D2 1 1 0
D3 1 1 0
D5 1 1 0
D6 1 1 0
DXE Phase
60 0 1 1
62 0 1 1
68 0 1 1
69 0 1 1
6A 0 1 1
70 0 1 1
71 0 1 1
72 0 1 1
78 0 1 1
79 0 1 1
7D 0 1 1
7E 0 1 1
90 1 0 0
91 1 0 0
92 1 0 0
Lower Nibble
1h 8h 4h 2h 1h
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
0 1 1 1 1
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
0 0 0 0 0
0 0 0 1 0
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 1 0 0 0
1 1 0 0 1
1 1 1 0 1
1 1 1 1 0
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
Description
Memory Installed
CPU PEIM (CPU Init)
CPU PEIM (Cache Init)
CPU BSP Select
CPU AP Init
CPU SMM Init
DXE IPL started
Memory POR check
Internal Use
Internal Use
Internal Use
Memory Early Init
Display DIMM info in debug mode
JEDEC Nvdimm training
Setup SVL and Scrambling
Internal Use
Check RAS support
Pmem ADR Init
Internal Use
Memory Late Init
Determine MRC boot mode
MKTME Early Init
SGX Early Init
Memory Margin Test
Internal Use
Internal Use
Offset Training Result
DXE Core started
DXE Setup Init
DXE PCI Host Bridge Init
DXE NB Init
DXE NB SMM Init
DXE SB Init
DXE SB SMM Init
DXE SB devices Init
DXE ACPI Init
DXE CSM Init
DXE Removable Media Detect
DXE Removable Media Detected
DXE BDS started
DXE BDS connect drivers
DXE PCI bus begin
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