Advantech PCM-3718 Series User Manual page 64

CNT = 0
STA = 0
C2, C1 & C0
If you set both SC1 and SC0 to 1 and STA to 0, the register selected by
C2 to C0 contains a byte which shows the status of the counter. The data
format of the counter read/write register then becomes:
BASE+12/13/14 - status read-back mode
Bit
Value OUT
OUT
NC
The pacer enable register, located at address BASE+10, has a close rela-
tionship with the counter operation. Refer to pages 32~33, Pacer Enable
Register, for the register data format. The TC0 bit enables and disables
the pacer. If TC0 is 0, the pacer is enabled. If TC0 is 1, the pacer is dis-
abled.
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Latch count of selected counter(s).
Latch status of selected counter(s).
Select counter for a read-back operation.
C2 = 1 select Counter 2
C1 = 1 select Counter 1
C0 = 1 select Counter 0
D7 D6 D5
NC RW1
Current status of counter output
Null count is 1 when the last count written to the
counter register has been loaded into the counting
element
D4 D3 D2
RW0 M2 M1
55
D1 D0
M0 BCD
Chapter 7