On-Board Socket Site Submenu - Xycom AHIP-370 Manual

AHIP-370 Manual
Enable Memory Gap
ECC Configuration
SERR Signal Conditions
8-bit I/O Recovery
16-bit I/O Recovery

On-board Socket Site Submenu

Advanced
On-board Socket Site
32-pin Socket Site Address
* 32-pin Socket Site Type
32-pin Socket Site I/O
↑↓
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Option
32-pin Socket Site Address
1
32-pin Socket Site Type
32-pin Socket Site I/O
1 = Visible only when Socket Site Address is "Enabled"
34
Allows creation at a 128K memory gap in conventional memory from 512K to 640K, or a
1MB memory gap in extended memory from 15 MB to 16 MB. Requires use of conven-
tional or extended memory. Default is [Disabled].
Allows configuration of Error Checking and Correction Memory. Requires ECC mem-
ory. Default is [Disabled]
Allows configuration of conditions upon which the SERR signal is to be asserted for
ECC memory. Requires ECC memory. Default is [Multiple bit].
Number of ISA clock cycles inserted between back-to-back I/O operations.
Xycom BIOS Setup Utility
[Disabled]
[SRAM]
[180h-181h]
Select Item
Figure 3-7. On-board Socket Site submenu
Table 3-7. On-board Socket Site submenu options
Description
Allows on-board 32-pin socket site to be disabled or mapped to a memory range.
Default is [Disabled].
Indicates type of memory installed in on-board 32-pin socket site. Default is [SRAM].
Allows configuration of I/O address used by on-board 32-pin socket site. Default
is [180h-181h].
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F9 Setup Defaults
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