AHIP-370 Manual
Registers
The AHIP-370 contains five I/O ports: 231h, 233h, 234h, and a user-definable port
(port 180/1h, 2E0/1h, 3E0/1h, or 300/1h). These ports are compatible with AHIP4+
and AHIP 6+.
Register 231h – Miscellaneous Control
Register 231h controls the LEDs and signals shown in the following table.
Bit
0
1
2
3
4
5*
6
7
*Note:
AT bus. This bit also enables the FLASH @C0000h when booting to FLASH.
Register 233h – Flash BIOS Control
Register 233h controls the signals shown in the following table.
Bit
0
1
2
3
4
5
6
7
20
Table 2- 7. Register 231h - CPU LED Port
LED/Signal
Result
Reserved
0
DOC 2000
1= Enables DOC 2000
Reserved
0
Reserved
0
Reserved
0
ENFLASHWR
1 = Enables Flash write
VGA_EN
1 = Enables on-board VGA
CLRCMS
1 = CMOS okay
0 = Clear CMOS
This bit must be 1 to make FLASH visible @D0000h when booting from
Table 2- 8. Register 233h - Flash BIOS Control Register
Signal
Result
FLA15
Flash address 15 - page control bit
FLA16
Flash address 16- page control bit
FLA17
Flash address 17 - page control bit
FLA18
Flash address 18 - page control bit
FPSEL0
Flat panel select bit 0
FPSEL1
Flat panel select bit 1
FPSEL2
Flat panel select bit 2
FPSEL3
Flat panel select bit 3
R/W
R
R/W
R
R
R
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R
R
R
R
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