Xycom AHIP-370 Manual page 15

The following table outlines the changes in jumper configurations between the
AHIP-370 and AHIP6:
AHIP6 AHIP-370
Jumper Jumper
J6 N/A
J1 J1
J2 J2
J3 J3
J4 J4
J5 N/A
J7 J7
J18 N/A
N/A J8
N/A J9
J8 J10
NA J14, 15, 16,
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Table 2- 2. Changes in Jumper Configuration
Description
Controls the speed of the CPU
A PB reset disabled
B PB reset enabled
A CPU will not clear CMOS on
power up
B CPU will clear CMOS
A Flat panel enabled
B CRT port enabled
A Normal operation
B Puts H8 in program mode
A Normal flash boot
B Recovery flash boot
A CPU boots from flash
B CPU boots from ROM
A Onboard video enabled
B Onboard video disabled
A The asserted state will enable
the RS-485 port.
B The negated state will enable
the RS-485 port.
A DTR is used to control the
RS-485 port.
B RTS is used to control the
RS-485 port.
Used to program Lattice
component.
OUT = Xycom Controller, PS/2
Mode
IN = Xycom Controller, Serial
Mode
Chapter Two - Installation
Comments
The socket370 implementation by Intel calls
for the CPU to define its own speed and not
be determined by jumpers. There are no
jumpers on the AHIP-370 for this purpose.
PB refers to an external pushbutton that may
be connected through the RS-232 interface.
See above.
The video is always enabled on the AHIP-370.
If an external VGA adapter is plugged into the
system, the BIOS will disable the onboard
chip.
Refers to the state of the modem control
signal selected by J9.
J8 and J9 function together to control the
RS485 port.
RS-485 TriState Control
On the AHIP6, the RS-485 is enabled by
asserting DTR. Two jumpers were added to
the AHIP-370 to allow either DTR or RTS to
control the RS-485 drives and determine
whether the asserted or negated state will
enable it.
Factory use only.
These jumpers allow the PS/2 AUX port and
interlink mouse to pass through the Xycom
controller.
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