Fuji Electric MICREX-SX Series User Manual page 21

Section 3 Programming
• Once "CLR" is turned ON, the current value is continuously cleared until "CLR" is turned OFF. The high-speed counter
(Hardware register) is immediately cleared when "CLR" is turned ON. However, the cleared value (hardware register value)
is reflected to the counter current value register (special register) at the end of the scan. When you need to read the cleared
value immediately, use the R_HSC instruction.
• When using the high-speed counter in delay timer mode, the initial value of "MASK" of the channel is ON (count disable).
Therefore, turn OFF (count enable) "MASK" after writing the counter set value.
• The figure below shows the operation timing of this instruction.
(Example of command pulse / direction signal [Application control] mode)
Command pulse
Counter current value
CH2 Hardware register
EN (Control request)
MASK (Count enable/disable)
CLR (Current value clear)
DIR (Direction signal)
* "CLR" signal operates by level. To stop clear operation, turn OFF the "CLR" signal by a user application.
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