Epson S5U13700B00C User Manual page 19

Note
S5U13700B00C Rev 1.0 Evaluation Board
Rev. 1.1
The following diagram shows the location of the host bus connectors (P1 and P2).
Connectors P1 and P2 are 2x2mm headers, 40 pins (20x2) each.
Bottom View
Figure 4-1: CPU Bus Connectors (P1 and P2) Location
For the pinout of connectors P1 and P2, refer to the schematics (see Section 6, "Schematic
Diagrams" on page 23).
1. When the board is connected to a PC using the Epson PC Card Extender, the signal
AS# is not used and R12 must NOT be populated. AS# input of S1D13700 should
be connected to HIOVDD by setting the dip switch (S1) position 6 to ON.
2. When the board is connected to different platforms, the Epson PC Card Extender is
not used. If using MC68K Family Bus interface, the signal AS# is used and it can be
provided to the P2 connector by populating R12 and the dip switch (S1) position 6
must be set to OFF position to disconnect AS# input from HIOVDD.
Seiko Epson Corporation
Technical Description
P1 and P2
CPU Bus Connectors
19