I²C Bus; Sm Bus - Congatec COM Express conga-TR4 User Manual

0Ah
0Bh (see Note 3)
Bus A
Bus A
Bus A
Bus A
Bus A
Bus A
Bus A
Bus A
Bus B
Note
1. The PCI Express Ports may only be visible if the PCI Express Port is set to "Enabled" in BIOS setup and a device is attached to the
corresponding PCI Express port on the carrier board.
2. The PCI Express Graphics Ports may only be visible if the PCI Express Graphics Port is set to "Enabled" in BIOS setup and a device is
attached to the corresponding PCI Express port on the carrier board.
3. The above table represents a case when a single function PCI Express device is connected to all possible slots on the carrier board. The
given bus numbers will change based on actual hardware configuration.
4. The PCI Express Port may only be visible if PEG port is set to 2 x4 and a device is attached to the corresponding PCI Express port on the
carrier board.
9.3 I²C Bus
There are no on-board resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions.
9.4

SM Bus

System Management (SM) bus signals are connected to the AMD Chipset and the SM bus is not intended to be used by off-board non-system
management devices. For more information about this subject please contact congatec technical support.
Copyright © 2018 congatec AG
00h 00h
00h 00h
00h 00h
00h 01h
00h 02h
00h 03h
00h 04h
00h 05h
00h 06h
00h 07h
00h 00h
Intel PCIe Ethernet Network on Module
PCI Express Port 7
Internal Internal GPU
Internal Display HD Audio Controller
Internal Cryptographic Coprocessor
Internal USB 3.1
Internal USB 3.1
Internal Audio Processor
Internal Audio Processor – HD Audio Controller
Internal SCSI PCIe
Internal SATA AHCI Mode
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