Broadcom Serial Control (Bsc) - Cypress WICED CYW920706WCDEVAL Hardware User's Manual

Option
Pin
32 F7
33 F7
34 F7
Table 9-4. CYW20706 PUART Bus-Configuration Options When PUART_RX Is on the Upper Pad Bank
PUART bus-configuration options presented in
For example, SPI1 master bus-configuration option 2 (from
PUART bus-configuration options (in
2 is used. So the remaining PUART bus-configuration options become 1–6, 15, and 16.
9.5 Broadcom Serial Control (BSC) (Compatible with I
CYW20706 supports a Broadcom Serial Control (BSC) interface.
Note: BSC is a proprietary Cypress interface that is compatible with I
The following information applies to the BSC interface:

There are three possible choices for the mapping of BSC signals (SDA and SCL) to CYW20706 pins as shown in the table
below. The parameter used for the wiced_hal_i2c_init function call for each selection of pins is also provided.
SDA
(Pin C7)
I2S_DIN/PCM_IN/SDA
(Pin A8) P35
(Pin E8) SFLASH_MOSI

The interface supports the following transfer types:

Read

Write

Combined write then read
Note: The BSC block generates a repeated START condition between the two parts of a combined transfer.

The maximum transaction length is 64 bytes.

Both low-speed and fast-mode slaves are supported at a maximum clock speed of 4000 kbps. The maximum clock speed
is 2400 kbps for slaves that use clock-cycle stretching.
Note: Clock speeds may be less than the speeds indicated above (for example, if an external pull-up resistor is used and
it affects transmission time).

Multi-master bus mode is not supported and, thus, CYW20706 must be the only bus master.

Only 7-bit slave addresses are supported.

Information on the API functions that support the interface is in wiced_hal_i2c.h.
1
These pins have a 4.7K pull up on the CYW920706WCDEVAL kit.
2
These pins cannot be used for BSC by default on the CYW920706CDEVAL kit because they are used for SPI communication with the
serial flash.
CYW920706WCDEVAL Hardware User Guide
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PUART_RX PUART_TX
LHL GPIO Pxx Pin
P25 G8
P25 G8
P25 G8
Table 9-4
Table 9-4) that use G8, F8, or F7 cannot be used if SPI1 master bus-configuration option
SCL
(Pin A8)
1
I2S_DOUT/PCM_OUT/SCL
(Pin B7) P37
2
(Pin D8) SFLASH_MISO
Table 9-5. BSC Signals Pins and Parameters
Doc. No.: 002-16535 Rev. **
Interface Signal Function Selection Restrictions and Considerations
PUART_RTS
LHL GPIO
Pin
Pxx
P24 C6
P24 D6
P24 D6
will be further reduced by the selected SPI1 bus-configuration option.
Table 9-2) requires digital I/O pins G8, F8, and F7. Therefore, all
2
C.
Configuration Parameter Name
WICED_I2C_SDA_I2S_DOUT_PCM_OUT_SCL_I2S_DIN_PCM_IN
1
WICED_I2C_SDA_P35_SCL_P37
2
WICED_I2C_SDA_SFLASH_MOSI_SCL_SFLASH_MISO
PUART_CTS
LHL GPIO
Pin
Pxx
P30 A8
P6 A8
P6 A8
2
C)
LHL GPIO
Pxx
P35
P3
P35
34