Digital I/O Pin Interface Mapping - Cypress WICED CYW920706WCDEVAL Hardware User's Manual

CYW20706 Pin
F8
G8
Note: Table 8-2
support all GPIOs. Check the module schematic and other documentation to determine which GPIOs are available.

8.1.2 Digital I/O Pin Interface Mapping

Table 8-3 shows the mapping of CYW20706 interfaces to the 12 digital I/O pins and the available GPIO_Pxx assignments.
This is the same information explained in
description of the selection choices available for an example pin.
To help understand
D6. If an alphanumeric string or an X appears in a signal-function column for a given pin, then that pin can support the signal
function. Using this logic, pin D6 can be configured to support one signal function from the following set of signal functions:
CYW920706WCDEVAL Hardware User Guide
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1
GPIO I/O Type
O
P36 I/O
I
I
O
I
O
O
P38 I/O
I
O
I
O
P4 I/O
I
I
O
I
O
P24 I/O
O
I
O
Table 8-2. CYW20706 Multiplexed GPIO_Pxx Interface Summary
provides GPIO information for the full capabilities of CYW20706. Some CYW20706-based modules may not
Table 8-2,
Table 8-3 consider the shaded portion of the table, which pertains to the signal-function selection for pin
Description
Signal Function Options
Peripheral UART TX output (PUART_TX)
General purpose, user-defined GPIO
A/D converter input (A/D input 3)
Z-coordinate output from a quadrature detector (QDZ0)
SPI1_CLK (master)
SPI1_CLK (slave)
Auxiliary clock output (ACLK0)
T/R switch control (~TX_PD)
General purpose, user-defined GPIO
A/D converter input (A/D input 1)
SPI1_MOSI (master)
SPI1_MOSI (slave)
Infrared learning output playback (IR_TX)
General purpose, user-defined GPIO
Y-coordinate output from a quadrature detector (QDY0)
Peripheral UART RX input (PUART_RX)
SPI1_MOSI (master)
SPI1_MOSI (slave)
Infrared learning output playback (IR_TX)
General purpose, user-defined GPIO
SPI1_CLK (master)
SPI1_CLK (slave)
Peripheral UART TX output (PUART_TX)
but in a more compact format for easier reference with the following
Doc. No.: 002-16535 Rev. **
7BGPIO Information
25