Cypress WICED CYW920706WCDEVAL Hardware User's Manual page 27

J22.8/
P3
A8
J23.6/
P29
J21.2
P35
J22.3/
B5
P15
J24.1
J22.4/
P11
B6
J23.5
P26
P2
B7 J22.5
P28
P37
J19.5/
P33
C5
J21.7
P27
J19.2/
C6
J23.4 P30
J22.7/
P12
J23.5/
C7
J21.1
J22.6/
P0
C8
J23.6
P34 P34
P6
D6 J19.1
P31
J19.4/
P25
F7
J21.6
P32
J19.6/
P36
F8
J21.8
P38
J19.3/
G8 P4
J21.5
P24
* This instance of P2 is SPI1_MOSI (master only).
An X in the red rectangle indicates that the associated signal functions do not involve any LHL GPIO signals.
The LHL GPIOs in the green rectangle indicate the associated signal functions are available only in those LHL GPIOs.
CYW920706WCDEVAL Hardware User Guide
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P3 P3
P35
P26
P2 P2 P2*
P33 P33
P27
P30
P0 P0
P6 P6
P31
P25 P25
P32 P32
P36
P38
P4 P4
P24 P24
P29
P35
P15 P15
P11 P11
P26
P28
P37 P37 P37
P33 P33
P27
P30
P12
P0 P0
P34
P31
P32 P32
P36 P36
P38 P38
P4
Table 8-3. Interface Mapping to the 12 Available Digital I/O Pins
Doc. No.: 002-16535 Rev. **
P29 P29
P15
P26 P26
P28 P28
P27 P27
P0
P34
P6
P36
X
P3
P35
P2
P37
P33
P34
P6
P32
P36
P4