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P9412 Evaluation Board Manual
2.1.2.4.
Interrupt Clear Registers, INT_Clear_L (0x3A), INT_Clear_H (0x3B)
Address
Register Field Name
and bit
0x3A [7]
STAT_VOUT_CLR
0x3A [6]
STAT_VRECT_CLR
0x3A [5]
MODECHANGE_CLR
0x3A [4]
OVER_VOLT_CLR
0x3A [3]
OVER_CURR_CLR
0x3A [2]
OVER_TEMP_CLR
0x3A [1]
Reserved
0x3A [0]
ADT_Error_CLR
0x3B [7]
Data Received_CLR
0x3B [6]
CD_ERROR_CLR
0x3B [5]
Reserved
0x3B [4]
PropModeStat_CLR
0x3B [3]
CD_MODECHANGE_
CLR
0x3B [2]
AC Missing _CLR
0x3B [1]
ADT Received_CLR
0x3B [0]
ADT Sent_CLR
Set bits in this register to clear corresponding interrupt flags. The register is self-cleared. Writing to this register
does not invoke the clear by itself. The user must set BIT 5 in System Command Register (0x4E) to trigger the
interrupt clear event (see System Command Register, SYS_CMND_L (0x4E), SYS_CMND_H (0x4F)).
2.1.2.5.
TRX System Operating Mode Register, Sys_Op_Mode (0x4C)
Address
Register Field Name
and bit
0x4C [7:4]
Reserved
0x4C [3:0]
Sys_Op_Mode
This register is cleared at entry to AC Missing State (DC power only), and will read back 0x0. This is the state
when power is provided by the user to Vrect, Vout, or CPout and no AC signal is detected on the rectifier inputs.
For Capacitor Divider mode status, see Capacitor Divider Mode Status Register, CDModeSts (0x100). For Tx
mode status see TX Status Registers, Status_L (0x34), Status_H (0x35).
2.1.2.6.
Over-Current Status Register, OC_Status (0xB5)
Address
Register Field Name
and bit
0xB5 [7:5]
Reserved
0xB5 [4]
CDIV_OC
0xB5 [3:1]
Reserved
0xB5 [0]
MLDO_OC
Rev.1.7
Jul.8.20
R/W
Default
Value
W
0
VOUT state change interrupt flag clear. AP writes "1" to clear the
corresponding Interrupt Registers' bit and this bit is self-cleared to "0" (by
MCU) afterwards.
W
0
AC power applied and stable interrupt flag clear
W
0
Mode Changed interrupt flag clear
W
0
Overvoltage condition ON/OFF interrupt flag clear
W
0
Overcurrent condition ON/OFF interrupt flag clear
W
0
Over-temperature condition ON/OFF interrupt flag clear
0
W
Reserved
ADT Error interrupt flag clear. AP writes "1" to clear the corresponding
W
0
Interrupt Registers' bit and this bit is self-cleared to "0" (by MCU) afterwards.
W
0
Tx data received interrupt flag clear
Capacitor Divider Error interrupt flag clear.
W
0
W
0
Reserved
Proprietary Mode Status interrupt flag clear.
W
0
W
0
Capacitor Divider Mode Changed interrupt flag clear.
W
0
AC Missing interrupt flag clear. Interrupt only generated after power up from
battery (external source different from AC power).
W
0
Tx ADT received interrupt flag clear.
W
0
Rx ADT sent interrupt flag clear.
R/W
Default
Value
R
0
Reserved
R
0000
0000 = AC Missing
0001 = WPC Basic Protocol
0010 = WPC Extended Protocol
0011 = Renesas Proprietary Protocol
1000 = TX Mode
1001 = TX FOD (Stop power transfer) / TX Conflict (Stop ping)
R/W
Default
Value
R
0
Reserved
R
0
"1" indicates an Over-Current condition in the Cap Divider circuit block.
Provides additional information on cause of the OC status or interrupt bit
being set. Bit is cleared when OC_INT is cleared.
R
0
Reserved
R
0
"1" indicates an Over-Current condition in the Main LDO circuit block.
Provides additional information on cause of the OC status or interrupt bit
being set. Bit is cleared when OC_INT is cleared.
Function and Description
Function and Description
Function and Description
Page 27
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