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Summary of Contents for Renesas PEB383 QFN
- Page 1 ® PEB383 (QFN) ™ Evaluation Board User Manual 602080_MA001_01 February 2010 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2009 Integrated Device Technology, Inc.
- Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
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Page 3: Table Of Contents
Contents About this Document........... . . 5 Related Information . - Page 4 Contents LEDs ................. . . 29 PEB383 (QFN) Evaluation Board User Manual Integrated Device Technology 602080_MA001_01...
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Page 5: About This Document
It can be used in conjunction with the PEB383 (QFN) Evaluation Board Schematics. Related Information • PEB383 User Manual • PEB383 (QFN) Evaluation Board Schematics • PEB383 QFN Board Design Guidelines • PCI Express Base Specification (Revision 1.1) • PCI Express CEM Specification (Revision 1.1) • PCI Express-to-PCI/PCI-X Bridge Specification (Revision 1.0) - Page 6 About this Document PEB383 (QFN) Evaluation Board User Manual Integrated Device Technology 602080_MA001_01 www.idt.com...
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Page 7: Board Design
Board Design Topics discussed include the following: • “Overview” on page 7 • “PCI Interface” on page 9 • “PCIe Interface” on page 10 • “Power Management” on page 10 • “Clock Management” on page 14 • “Other Interfaces” on page 15 •... - Page 8 1. Board Design Figure 1: Evaluation Board Block Diagram PCI Express Card Edge X1 1x SerDes SMA Points LA Probe SerDes Path Resistor Select ATX Connectors PCIe Power Management PEB383 Clock EEPROM Header EEPROM JTAG Management 3.3V PCI 32-bit Connector Slot 0 3.3V PCI 32-bit Connector Slot 1...
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Page 9: Pci Interface
1. Board Design PCI Interface 1.2.1 Overview The PCI Interface is implemented on the board with four slots, in which one is an R/A mounted connector on the top of the board. All PCI connectors are compliant with the PCI 3.0 specification. Appropriate clearance is provided such that up to four PCI cards can be inserted for testing while the board is in an open-chassis standard ATX case. -
Page 10: Pcie Interface
1. Board Design Table 2: PCI Pull-up Signals (Continued) Signal Description PCI_STOP# Control signal PCI_SERR# System error PCI_PERR# Parity error PCI_DEVSEL# Device select line PCI_INT#[A:D] Interrupt line PCI_PME# PCI Power Management Event occurred PCIe Interface The PEB383 evaluation board implements a single lane PCIe Interface. It is designed to connect to a PCIe system with a standard x1 finger connector. -
Page 11: Power Requirements
1. Board Design 1.4.2 Power Requirements The power requirements and implementation for the PEB383 is as follows. Table 3: PEB383 Power Requirements Supply Name Symbol Supplied Source Device Core 1.2V_384 DC/DC switching regulator w/Enable pin PCIe 1.0V Core 1.2V_A_384 Passive Filter PCI 3.3V supply 3.3V_384 Power switch w optional Ferrite filter to reduce... - Page 12 1. Board Design 1.4.2.2 The PCISIG defines the power rules regarding PCI cards as a maximum of 25 Watts per card (All power rails combined power draw). The individual current limits on voltage rails are included in Table Table 5: PCI Connector Current Limits Rail Current 3.3V...
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Page 13: Power Sequencing
1. Board Design 1.4.3 Power Sequencing On power-up, the board’s power sequence is as follows: 1. 1.2V powered on 2. PCI I/O slot power and pull-ups, and 3.3V 12V/-12V/5V PCI are not sequence controlled. 1.4.4 System Power Design Figure 2 illustrates the power distribution for the riser card. -
Page 14: Pci Vaux (Pci Auxiliary) Support
1. Board Design 1.4.5 PCI Vaux (PCI Auxiliary) Support PCI connectors are provided with a 3.3V supply to the vaux pins only during operation. There is no support for this power supply in standby mode. This feature is not documented in the PEB383 evaluation board schematic. -
Page 15: System Clock Distribution
1. Board Design 1.5.2 System Clock Distribution The following figure shows the distribution of the system clock on the PEB383 evaluation board. Figure 3: System Clock Distribution PCIe System PCIe_REFCLK ICS557-01 PCIe_SYS_CLK Config PCI_EXT_CLK[1] ICS87604I PCI_EXT_CLK[0] PCIe_GEN_CLK ANALOG PEB383 PCI_FBK_CLK Passive PCI Clock PCIe_REF_CLK... -
Page 16: Hardware Reset
1. Board Design Hardware Reset The following figure shows the reset options of the PEB383 evaluation board. Figure 4: Board Reset Reset PUSHBUTTON PCIe_PERSTn Controller SYS_PCIe_PERSTn PCIe Edge Connector X1 Three levels of reset are available: • Cold reset – This reset is applied during power up. System (card edge) PCIe_PERSTn is muxed with the board’s reset controller. -
Page 17: Configurable Options
Configurable Options Topics discussed include the following: • “Switches” on page 17 • “Shunt Jumpers” on page 22 • “Debug Headers” on page 24 • “Connectors” on page 27 • “LEDs” on page 29 Switches 2.1.1 DIP Switches Switches S1 to S6 combine four, small slide switches identified with numbers 1 to 4 (see Table 7 individual switch definition). - Page 18 2. Configurable Options Figure 6: Switch Locations Tsi382 (LQFP) Evaluation Board User Manual Integrated Device Technology 602020_MA001_02 www.idt.com...
- Page 19 2. Configurable Options Switch S1 is used to manually set PCI bus modes. Table 7: S1 Settings Switch Default Number Description Setting On/Off Setting M66EN ON = Connects M66EN to all cards OFF = Forces M66EN high if S1.2 OFF M66EN ON = Forces M66EN to GND OFF = Disables forcing M66EN to GND...
- Page 20 2. Configurable Options Switch S4 controls the external clock PLL. Table 9: S4 Settings Switch Default Number Description Setting On/Off Setting PLL Reset ON = PLL in reset. PLL clock outputs are low. OFF = PLL is active and clock outputs are enabled. XTAL select ON = Clock source for PLL is reference clock from connector OFF = Clock source for PLL is a 25-MHz oscillator.
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Page 21: Push Button
2. Configurable Options Switch S6 configures PEB383’s power-up options. Table 11: S6 Settings Switch Default Number Description Setting On/Off Setting No function Internal ON = Internal arbiter is enabled arbiter option OFF = Internal arbiter is disabled No function PCI PLL ON = PLL is enabled bypass OFF = PLL is bypassed... -
Page 22: Shunt Jumpers
2. Configurable Options Shunt Jumpers Shunt jumpers control special features on the evaluation board (see Figure 7). These jumpers are explained in the following sub-sections. Figure 7: Shunt Jumper Locations Tsi382 (LQFP) Evaluation Board User Manual Integrated Device Technology 602020_MA001_02 www.idt.com... -
Page 23: J6 Shunt Jumper
2. Configurable Options 2.2.1 J6 Shunt Jumper J6 is used to bypass the On/Off push button to enable the ATX power supply. Table 12: J6 Shunt Jumper Setting Jumper Default Setting Setting Function Installed Removed Forces ATX power supply ON. Removed Normal operation, ATX power supply is turned On/OFF from push button. -
Page 24: Debug Headers
2. Configurable Options Debug Headers Debug headers are used to connect to signals on the evaluation board. This section provides header pinouts. Figure 8: Debug Header Locations Tsi382 (LQFP) Evaluation Board User Manual Integrated Device Technology 602020_MA001_02 www.idt.com... -
Page 25: J22 Peb383 Jtag
2. Configurable Options 2.3.1 J22 PEB383 JTAG Table 13: J22 Pin Assignment Number Signal Assignment Pin Location 3.3V 3.3V Integrated Device Technology Tsi382 (LQFP) Evaluation Board User Manual www.idt.com 602020_MA001_02... -
Page 26: J23 Logic Analyzer Pads
2. Configurable Options 2.3.2 J23 Logic Analyzer PADs Table 14: J23 Pin Assignment Number Signal Assignment Pin Location PCIE_RXD_EDG_P0 PCIE_RXD_EDG_N0 PCIE_TXD_EDG_P0 PCIE_TXD_EDG_N0 Tsi382 (LQFP) Evaluation Board User Manual Integrated Device Technology 602020_MA001_02 www.idt.com... -
Page 27: Connectors
2. Configurable Options Connectors Figure 9: Board Connector Locations J2 (Slot 0) J36 (Slot 1) J1 (Slot 2) J37 (Slot 3) 2.4.1 J1, J2, J36, J37 Connectors These connectors are used to connect a plug-in card to the PEB383’s PCI Interface. The connectors’ pin assignments are as per the PCI standard for 32-bit connectors. -
Page 28: J3 Atx Power Connector
2. Configurable Options 2.4.2 J3 ATX Power Connector A standard ATX power supply can be used to power up the board when used stand alone (not plugged into a PCIe system). Table 15: J3 Pin Assignment Number Signal Assignment J3 Pin Location 3.3V 3.3V N.C. - Page 29 2. Configurable Options LEDs Figure 10: LED Locations D2-D8 Integrated Device Technology Tsi382 (LQFP) Evaluation Board User Manual www.idt.com 602020_MA001_02...
- Page 30 2. Configurable Options Tsi382 (LQFP) Evaluation Board User Manual Integrated Device Technology 602020_MA001_02 www.idt.com...
- Page 31 CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 email: ssdhelp@idt.com San Jose, CA 95138 fax: 408-284-2775 phone: 408-284-8208 www.idt.com Document: 602080_MA001_01 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice.
- Page 32 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
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