Renesas P9412 Manual page 3

P9412 Evaluation Board Manual
2.1.5.7.
2.1.5.8.
2.1.5.9.
2.1.5.10.
2.1.5.11.
2.1.5.12.
2.1.5.13.
2.1.5.14.
2.1.5.15.
2.1.5.16.
2.1.5.17.
2.1.5.18.
2.1.5.19.
2.1.6. HW Control and Monitor Registers ....................................................................................... 37
2.1.6.1.
2.1.6.2.
2.1.6.3.
2.1.6.4.
2.1.6.5.
2.1.6.6.
2.1.6.7.
2.1.6.8.
2.1.6.9.
2.1.6.10.
2.1.6.11.
2.1.6.12.
2.1.6.13.
2.1.7. Vrect Control Registers ......................................................................................................... 41
2.1.7.1.
2.1.7.2.
2.1.7.3.
2.1.7.4.
2.1.7.5.
2.1.7.6.
2.1.8. Capacitor Divider Registers .................................................................................................. 42
2.1.8.1.
2.1.8.2.
2.1.8.3.
2.1.8.4.
2.1.8.5.
2.1.9. Foreign Object Detection Registers ...................................................................................... 43
2.1.9.1.
2.1.9.2.
2.1.9.3.
2.1.9.4.
2.1.9.5.
2.1.10. WPC Basic and Extended Protocol Registers ...................................................................... 45
2.1.10.1.
Rev.1.7
Jul.8.20
TRX Data Value 1~2 Register (PropPkt Received), TRX_Data_Value1_2_In (0x59, 0x5A) ........... 34
Com Channel Send Size Register, CC_Send_Size_L (0x140), CC_Send_Size_H (0x141) ........... 34
Com Channel Send Index Register, CC_Send_Index_L (0x142), CC_Send_Index_H (0x143) ...... 34
Com Channel Receive Size Register, CC_Recv_Size_L (0x144), CC_Recv_Size_H (0x145) ..... 35
Com Channel Receive Index Reg., CC_Recv_Index_L (0x146), CC_Recv_Index_H (0x147)...... 35
Com Channel Status Register, CC_Status (0x148) ....................................................................... 35
Pending Packets Register, Pend_Pkts (0x149) ............................................................................. 35
ADT Packet Time Out Register, ADT_Timeout_PKT (0x150) ....................................................... 35
ADT Stream Time Out Register, ADT_Timeout_STR (0x151) ...................................................... 35
ADT Error Code Register, ADT_Error_Code (0x14D) ................................................................... 36
ADT Buffer Registers, (0x0800 ~ 0x0FFF) .................................................................................... 36
Frequency Shift Keyed modulation (FSK) Transmitter to Receiver Communication ..................... 37
FSK Communication Protocol ....................................................................................................... 37
Ping Frequency Register, PingFreq_L (0x6A), PingFreq_H (0x6B) ................................................ 37
HW Flag Register, HW_Flag (0x81) ................................................................................................ 38
Over Voltage Protection Register, OV_Set (0xB3) .......................................................................... 38
RX Mode Communication Modulation FET Register, CMFET_L (0xF4), CMFET_H (0xF5) ........... 38
RX Mode AFC Communication Modulation FET Register, AFC_CMFET (0xB2) ............................ 38
RX Mode High Vout Communication Modulation FET Register, HiVout_CMFET (0x11B) .............. 39
Align X Register, AlignX (0xB0) ....................................................................................................... 39
Align Y Register, AlignY (0xB1) ....................................................................................................... 39
Align adc Offset Registers, AlignAdcOffX (0x164), AlignAdcOffY (0x165) ...................................... 40
Align Slope1 Registers, AlignSlope1X (0x166), AlignSlope1Y (0x167) ......................................... 40
Align Slope2 Registers, AlignSlope2X (0x168), AlignSlope2Y (0x169) ......................................... 40
Align Offset Registers, AlignOffX (0x16A), AlignOffY (0x16B) ....................................................... 41
Align Threshold Registers, AlignThreshX (0x16C), AlignThreshY (0x16D) ................................... 41
Target_Vrect Register, Vrect_Target_L(0x90), VrectTarget_H (0x91) ............................................ 41
Vrect Knee Register, PwrKnee (0x92) ............................................................................................. 41
Vrect Correction Factor Register, VrCorrFactor (0x93) ................................................................... 42
Vrect Maximum Correction Register, VrMaxCorr_L (0x94), VrMaxCorr_H (0x95) .......................... 42
Vrect Minimum Correction Register, VrMinCorr_L (0x96), VrMinCorr_H (0x97) ............................. 42
Vrect Adjust Register, VRectAdj (0x5E) .......................................................................................... 42
Capacitor Divider Mode Status Register, CDModeSts (0x100) ....................................................... 42
Capacitor Divider Mode Request Register, CDModeReq (0x101) ................................................... 42
TRX CPout Voltage Registers, VCPout_L (0x10C), VCPout_H (0x10D)......................................... 43
Capacitor Divider Vout Threshold Reg., CD_Vout_Thd_L (0x10A), CD_Vout_Thd _H (0x10B) ..... 43
Capacitor Divider Frequency Set Register, CD_Freq_L (0x108), CD_Freq _H (0x109) .................. 43
RX FOD Adjustable Parameters Registers, (0x70 ~ 0x7F) ............................................................. 43
TX FOD Threshold Registers, TX_FOD_Thrsh_L (0xD4), TX_FOD_Thrsh_H (0xD5) .................... 44
TX FOD Gain Register, TX_FOD_Gain (0xD1) ............................................................................... 44
TX FOD Offset Registers, TX_FOD_Offset_L (0xD2), TX_FOD_Offset_H (0xD3) ......................... 44
TX FOD Offset Option Register, FOD_OffsetOpt (0XA3) ................................................................ 44
EPP Q-Factor Register, EPP_Q_Factor (0x83) ............................................................................. 45
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