Renesas P9412 Manual page 4

P9412 Evaluation Board Manual
2.1.10.2.
2.1.10.3.
2.1.10.4.
2.1.10.5.
2.1.10.6.
2.1.10.7.
2.1.10.8.
2.1.10.9.
2.1.10.10.
2.1.10.11.
2.1.10.12.
2.1.10.13.
2.1.10.14.
2.1.10.15.
2.1.10.16.
2.1.10.17.
2.1.10.18.
2.1.10.19.
2.1.10.20.
2.1.10.21.
2.1.10.22.
2.1.10.23.
2.1.11. Proprietary High-Power Protocol Registers .......................................................................... 50
2.1.11.1.
2.1.11.2.
2.1.11.3.
2.1.11.4.
2.1.11.5.
2.1.11.6.
2.1.12. TX Mode Registers ............................................................................................................... 54
2.1.12.1.
2.1.12.2.
2.1.12.3.
2.1.12.4.
2.1.12.5.
2.1.12.6.
2.1.12.7.
2.1.12.8.
2.1.12.9.
2.1.12.10.
2.1.12.11.
2.1.12.12.
2.1.12.13.
2.1.12.14.
2.1.12.15.
2.1.12.16.
2.1.12.17.
2.1.12.18.
Rev.1.7
Jul.8.20
EPP Q-Factor A Register, EPP_Q_Fact_A (0x138) ...................................................................... 46
EPP Q-Factor B Register, EPP_Q_Fact_B (0x139) ...................................................................... 46
EPP TX Guaranteed Power Register, EPP_TXGuarPwr (0x84) ................................................... 46
EPP TX Potential Power Register, EPP_TXPotentPwr (0x85) ...................................................... 46
EPP TX Capability Flag Register, EPP_TXCapaFlag (0x86) ........................................................ 46
EPP Renegotiation Status Register, EPP_RN_Sts (0x87) ............................................................ 46
EPP Current RPP Header Register, MPCur_RPP (0x88) ............................................................. 47
EPP Current Negotiated Power Register, MPCur_NegPwr (0x89) ................................................ 47
EPP Current Maximum Power Register, MPCur_MaxPwr (0x8A) ............................................... 47
EPP Current FSK Modulation Register, MPCur_FSK (0x8B) ...................................................... 47
EPP Request RPP Header Register, MPReq_RPP (0x8C) ......................................................... 47
EPP Request Re-Negotiated Power Register, MPReq_NegPwr (0x8D) ..................................... 47
EPP Request Maximum Power Register, MPReq_MaxPwr (0x8E) ............................................. 47
EPP Request FSK Modulation Register, MPReq_FSK (0x8F) .................................................... 48
WPC Spec Revision Register, WPC_SpecRev (0xB9) ................................................................ 48
EPP Rx Manufacturer Code Reg., MpRxManufCode_L (0xBA), MpRxManufCode_H (0xBB) .... 48
WPC Identification Register, WPC_ID (0xE0 ~ 0XE3) ................................................................ 48
Extended Identification Packet Register, WPC_ExtID (0xE4 ~ 0xEB) ......................................... 49
Signal Strength Packet Register, SSPValue (0xB4) .................................................................... 49
Control Error Packet Register, CEPValue (0x5F) ........................................................................ 49
RX Power Register, Rx_Pwr_L (0xCE), Rx_Pwr_H (0xCF) ........................................................ 49
WPC Manufacturer ID Register, WPC_ManufID_L (0x15E), WPC_ManufID_H (0x15F) ............ 50
Proprietary Tx Potential Power Register, PropTxPotenPwr (0xC4) ............................................... 53
Proprietary Requested Power Register, PropReqPwr (0xC5) ....................................................... 53
Proprietary Current Power Register, PropCurrPwr (0xC6) ............................................................ 53
Proprietary Negotiated Power Step Size Register, PropModePwrStep (0xC7) ............................. 53
Proprietary Mode Status Register, PropModeStatus (0xC8) ......................................................... 53
Proprietary Mode Error Register, PropErrStatus (0xC9) ................................................................ 53
TX Status Registers, Status_L (0x34), Status_H (0x35)................................................................ 54
TX Interrupt Registers, INT_L (0x36), INT_H (0x37) ..................................................................... 54
TX Interrupt Enable Registers, INT_Enable_L (0x38), INT_Enable_H (0x39) ............................... 55
TX Interrupt Clear Registers, INT_Clear_L (0x3A), INT_Clear_H (0x3B) ...................................... 56
System TX Command Register, TX_CMND (0x4D) ...................................................................... 56
TX Mode System Command Register, TxSysCmnd_L (0x4E), TxSysCmnd_H (0x4F) ................. 57
TX Mode CEP Threshold Register, TxCepThrshVal (0xD6) .......................................................... 57
TX Mode CEP Threshold Count Limit Register, TxCepThrshCntLmt (0xD7) ................................ 57
TX Mode API Current Limit Registers, I_API_Limit_L (0x56), I_API_Limit_H (0x57) .................... 58
TX Mode API Current Hysteresis Register, I_API_Hys (0x82) .................................................... 59
TX Mode API Current Limit Offset Registers, I_API_Offset_L (0xF6), I_API_Offset_H (0xF7) ... 59
TX Ping Frequency (Period) Register, PingFreqPer_L (0x90), PingFreqPer_H (0x91) ............... 59
TX Ping Duty Cycle Register, PingDC (0x92) .............................................................................. 59
TX Minimum Duty Cycle Register, MinDC (0x93) ........................................................................ 59
TX Minimum Frequency (Period) Register, MinFreqPer_L (0x94), MinFreqPer_H (0x95) .......... 60
TX Maximum Frequency (Period) Register, MaxFreqPer_L (0x96), MaxFreqPer_H (0x97) ....... 60
TX Mode Operating Period Register, TxPeriod_L (0xA4), TxPeriod_H (0xA5) ........................... 60
TX Mode Operating Duty Cycle Register, TxDuty (0xA6) ............................................................ 60
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