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Renesas P9412 Manuals
Manuals and User Guides for Renesas P9412. We have
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Renesas P9412 manuals available for free PDF download: Manual, Layout Manual
Renesas P9412 Manual (75 pages)
Brand:
Renesas
| Category:
Motherboard
| Size: 3.23 MB
Table of Contents
Figure 1. P9412 CSP Demo Board V1.3
1
Table of Contents
2
1 Usage Guide
7
Quick-Start Guide for Rx and Tx Mode Operation
7
Figure 2. Capacitor Divider Mode Transition Sequence
7
Using the Windows GUI
8
Using the GUI to Program the P9412
8
Figure 3. GUI Software
8
Figure 4. FTDI USB-I2C Bridge Connected to I2C Terminal J3 of P9412 CSP Trx Demo Board
8
Figure 5. Initial Screen of P9412 GUI
9
Figure 6. USB-Bridge Is Detected, P9412 Is Not Connected
9
Figure 7. P9412 MTP Programming Using I C Slave Device Address 0X3C
10
Figure 8. MTP Programming Successful
10
Figure 9. GUI Detects an Unprogrammed Part and Issues a Warning
11
Figure 10. Firmware Program Verification Success
11
Using the GUI to Read / Write to Registers
12
Figure 11. Verify FW Revision and Date Code
12
Figure 12. I2C Read / Write Registers
13
Figure 13. Basic 1 Tab, after a "Read 1 Time" Operation
13
Figure 14. VOUT Adjustments Can be Made in Three Ways
14
Using the GUI to Run in High Power Capacitor Divider Mode
15
Figure 15. Check Cap Divider Mode
15
Figure 16. Enable Cap Divider Mode Operation
16
Figure 17. P9412 Successfully Enters Cap DIV. Mode and Is Ready to Transition to High-Power Operation
16
Figure 18. P9412 Transition to High Power Operation
17
Figure 19. Using the GUI to Manually Increase the RX Vout Voltage
17
Using the GUI to Run in TX Mode
18
Figure 20. Using the GUI to Manually Decrease the RX Vout Voltage
18
Figure 21. Basic Registers Initial Read Back; before TX Mode Entry
19
Figure 22. Tx Mode Entry, Without an Rx Placed on the P9412 Coil; Vrect and Vout Voltage Read Back ~7V
19
Figure 23. Tx Mode, with an Rx Placed on the P9412 Coil; Use the GUI to Monitor the Status
20
Figure 24. Exit Tx Mode, with an Rx Placed on the P9412 Coil; Use the GUI to Send Exit Command
20
I 2 C Function
21
Figure 25. Verify Exit TX Mode; Use the GUI to Read Mode
21
Figure 26. I2C Read Protocol Using P9412
21
Figure 27. I2C Write Protocol Using P9412
22
I2C Read Back of MTP Contents
22
2 Registers
23
Identification and Revision Registers
23
Chip ID Register, Chip_Id_L (0X00), Chip_Id_H (0X01)
23
Chip Revision and Font Register, Chip_Rev (0X02)
23
Customer ID Register, Customer ID (0X03)
23
Firmware Major Rev. Registers, Fw_Major_Rev_L (0X04), Fw_Major_Rev_H (0X05)
23
Firmware Minor Rev. Registers, Minor_Rev_L (0X06), Fw_Minor_Rev_H (0X07)
23
Firmware Date/Time Registers, Fw_Date_Code (0X 08~13), Fw_Timer_Code (0X 14~1B)
23
Configuration Major Revision Registers, Cfg_Major_Rev (0X1C)
24
Configuration Minor Revision Registers, Cfg_Minor_Rev (0X1D)
24
Reference Design Version Register, Refdesignver (0X4A)
24
Status and Interrupt Registers
25
Status Registers, Status_L (0X34), Status_H (0X35)
25
Interrupt Registers, INT_L (0X36), INT_H (0X37)
25
Interrupt Enable Registers, Int_Enable_L (0X38), Int_Enable_H (0X39)
26
Interrupt Clear Registers, Int_Clear_L (0X3A), Int_Clear_H (0X3B)
27
TRX System Operating Mode Register, Sys_Op_Mode (0X4C)
27
Over-Current Status Register, Oc_Status (0Xb5)
27
Battery Status and Power Transfer Registers
28
Charge Status Register, Chg_Status (0X3E)
28
End of Power Transfer Register, Ept_Code (0X3F)
28
Operation Parameters Registers
28
Vout Set Register, Vout_Set_L (0X6C), Vout_Set_H (0X6D)
28
TRX Vout Voltage Registers, Vout_L (0X42), Vout_H (0X43)
29
Iout Limit Set Register (0X3D)
29
TRX Iout / Iin Value Registers, Iout / Iiin_L (0X44), Iout / Iin_H (0X45)
29
TRX Vrect Voltage Registers, Vrect_L (0X40), Vrect_H (0X41)
29
TRX die Temperature Registers, Dietemp_L (0X46), Dietemp_H (0X47)
29
TRX AC Frequency Registers, Ac_Freq_L (0X48), Ac_Freq_H (0X49)
29
Command and Communication Registers
30
System Command Register, SYS_CMND_L (0X4E), SYS_CMND_H (0X4F)
30
Config Table Command Register, Config_Cmnd (0Xca)
30
TRX Header Register (Proppkt Send), Trx_Header_Out (0X50)
32
TRX Data Value1 Register (Proppkt Send), Trx_Data_Value1_Out (0X51)
33
TRX Data Value 2~5 Reg. (Proppkt Send), Trx_Data_Value2_5_Out (0X52, 0X53, 0X54, 0X55)
33
TRX Header Register (Proppkt Received), Trx_Header_In (0X58)
34
TRX Data Value 1~2 Register (Proppkt Received), Trx_Data_Value1_2_In (0X59, 0X5A)
34
Com Channel Send Size Register, Cc_Send_Size_L (0X140), Cc_Send_Size_H (0X141)
34
Com Channel Send Index Register, Cc_Send_Index_L (0X142), Cc_Send_Index_H (0X143)
34
Com Channel Receive Size Register, Cc_Recv_Size_L (0X144), Cc_Recv_Size_H (0X145)
35
Com Channel Receive Index Reg., Cc_Recv_Index_L (0X146), Cc_Recv_Index_H (0X147)
35
Com Channel Status Register, Cc_Status (0X148)
35
Pending Packets Register, Pend_Pkts (0X149)
35
ADT Packet Time out Register, Adt_Timeout_Pkt (0X150)
35
ADT Stream Time out Register, Adt_Timeout_Str (0X151)
35
ADT Error Code Register, Adt_Error_Code (0X14D)
36
ADT Buffer Registers, (0X0800 ~ 0X0Fff)
36
2.1.5.18. Frequency Shift Keyed Modulation (FSK) Transmitter to Receiver Communication
37
2.1.5.19. FSK Communication Protocol
37
HW Control and Monitor Registers
37
Ping Frequency Register, Pingfreq_L (0X6A), Pingfreq_H (0X6B)
37
Figure 28. Example of Differential Bi-Phase Encoding
37
Figure 29. Example of Asynchronous Serial Byte Format
37
HW Flag Register, Hw_Flag (0X81)
38
Over Voltage Protection Register, Ov_Set (0Xb3)
38
RX Mode Communication Modulation FET Register, CMFET_L (0Xf4), CMFET_H (0Xf5)
38
RX Mode AFC Communication Modulation FET Register, AFC_CMFET (0Xb2)
38
RX Mode High Vout Communication Modulation FET Register, Hivout_Cmfet (0X11B)
39
Align X Register, Alignx (0Xb0)
39
Align y Register, Aligny (0Xb1)
39
Align Adc Offset Registers, Alignadcoffx (0X164), Alignadcoffy (0X165)
40
Align Slope1 Registers, Alignslope1X (0X166), Alignslope1Y (0X167)
40
Align Slope2 Registers, Alignslope2X (0X168), Alignslope2Y (0X169)
40
Align Offset Registers, Alignoffx (0X16A), Alignoffy (0X16B)
41
Align Threshold Registers, Alignthreshx (0X16C), Alignthreshy (0X16D)
41
Vrect Control Registers
41
Target_Vrect Register, Vrect_Target_L(0X90), Vrecttarget_H (0X91)
41
Vrect Knee Register, Pwrknee (0X92)
41
Vrect Correction Factor Register, Vrcorrfactor (0X93)
42
Vrect Maximum Correction Register, Vrmaxcorr_L (0X94), Vrmaxcorr_H (0X95)
42
Vrect Minimum Correction Register, Vrmincorr_L (0X96), Vrmincorr_H (0X97)
42
Vrect Adjust Register, Vrectadj (0X5E)
42
Capacitor Divider Registers
42
Capacitor Divider Mode Status Register, Cdmodests (0X100)
42
Capacitor Divider Mode Request Register, Cdmodereq (0X101)
42
TRX Cpout Voltage Registers, Vcpout_L (0X10C), Vcpout_H (0X10D)
43
Capacitor Divider Vout Threshold Reg., Cd_Vout_Thd_L (0X10A), Cd_Vout_Thd
43
Capacitor Divider Frequency Set Register, Cd_Freq_L (0X108), Cd_Freq
43
Foreign Object Detection Registers
43
RX FOD Adjustable Parameters Registers, (0X70 ~ 0X7F)
43
TX FOD Threshold Registers, Tx_Fod_Thrsh_L (0Xd4), Tx_Fod_Thrsh_H (0Xd5)
44
TX FOD Gain Register, Tx_Fod_Gain (0Xd1)
44
TX FOD Offset Registers, Tx_Fod_Offset_L (0Xd2), Tx_Fod_Offset_H (0Xd3)
44
TX FOD Offset Option Register, Fod_Offsetopt (0XA3)
44
WPC Basic and Extended Protocol Registers
45
EPP Q-Factor Register, Epp_Q_Factor (0X83)
45
EPP Q-Factor a Register, Epp_Q_Fact_A (0X138)
46
EPP Q-Factor B Register, Epp_Q_Fact_B (0X139)
46
EPP TX Guaranteed Power Register, Epp_Txguarpwr (0X84)
46
EPP TX Potential Power Register, Epp_Txpotentpwr (0X85)
46
EPP TX Capability Flag Register, Epp_Txcapaflag (0X86)
46
EPP Renegotiation Status Register, Epp_Rn_Sts (0X87)
46
EPP Current RPP Header Register, Mpcur_Rpp (0X88)
47
EPP Current Negotiated Power Register, Mpcur_Negpwr (0X89)
47
EPP Current Maximum Power Register, Mpcur_Maxpwr (0X8A)
47
EPP Current FSK Modulation Register, Mpcur_Fsk (0X8B)
47
EPP Request RPP Header Register, Mpreq_Rpp (0X8C)
47
EPP Request Re-Negotiated Power Register, Mpreq_Negpwr (0X8D)
47
EPP Request Maximum Power Register, Mpreq_Maxpwr (0X8E)
47
EPP Request FSK Modulation Register, Mpreq_Fsk (0X8F)
48
WPC Spec Revision Register, Wpc_Specrev (0Xb9)
48
EPP Rx Manufacturer Code Reg., Mprxmanufcode_L (0Xba), Mprxmanufcode_H (0Xbb)
48
WPC Identification Register, WPC_ID (0Xe0 ~ 0XE3)
48
Extended Identification Packet Register, Wpc_Extid (0Xe4 ~ 0Xeb)
49
Signal Strength Packet Register, Sspvalue (0Xb4)
49
Control Error Packet Register, Cepvalue (0X5F)
49
RX Power Register, Rx_Pwr_L (0Xce), Rx_Pwr_H (0Xcf)
49
WPC Manufacturer ID Register, Wpc_Manufid_L (0X15E), Wpc_Manufid_H (0X15F)
50
Proprietary High-Power Protocol Registers
50
Figure 30. Proprietary High Power Protocol Flow Chart
52
Proprietary Current Power Register, Propcurrpwr (0Xc6)
53
Proprietary Mode Error Register, Properrstatus (0Xc9)
53
Proprietary Mode Status Register, Propmodestatus (0Xc8)
53
Proprietary Negotiated Power Step Size Register, Propmodepwrstep (0Xc7)
53
Proprietary Requested Power Register, Propreqpwr (0Xc5)
53
Proprietary Tx Potential Power Register, Proptxpotenpwr (0Xc4)
53
TX Mode Registers
54
TX Status Registers, Status_L (0X34), Status_H (0X35)
54
TX Interrupt Registers, INT_L (0X36), INT_H (0X37)
54
TX Interrupt Enable Registers, Int_Enable_L (0X38), Int_Enable_H (0X39)
55
TX Interrupt Clear Registers, Int_Clear_L (0X3A), Int_Clear_H (0X3B)
56
System TX Command Register, TX_CMND (0X4D)
56
TX Mode System Command Register, Txsyscmnd_L (0X4E), Txsyscmnd_H (0X4F)
57
TX Mode CEP Threshold Register, Txcepthrshval (0Xd6)
57
TX Mode CEP Threshold Count Limit Register, Txcepthrshcntlmt (0Xd7)
57
TX Mode API Current Limit Registers, I_Api_Limit_L (0X56), I_Api_Limit_H (0X57)
58
TX Mode API Current Hysteresis Register, I_Api_Hys (0X82)
59
TX Mode API Current Limit Offset Registers, I_Api_Offset_L (0Xf6), I_Api_Offset_H (0Xf7)
59
TX Ping Frequency (Period) Register, Pingfreqper_L (0X90), Pingfreqper_H (0X91)
59
TX Ping Duty Cycle Register, Pingdc (0X92)
59
TX Minimum Duty Cycle Register, Mindc (0X93)
59
TX Minimum Frequency (Period) Register, Minfreqper_L (0X94), Minfreqper_H (0X95)
60
TX Maximum Frequency (Period) Register, Maxfreqper_L (0X96), Maxfreqper_H (0X97)
60
TX Mode Operating Period Register, Txperiod_L (0Xa4), Txperiod_H (0Xa5)
60
TX Mode Operating Duty Cycle Register, Txduty (0Xa6)
60
TX Mode Over-Voltage Protection Register, Tx_Ovp_L (0X9E), TX_OVP_H (0X9F)
60
TX Mode Over-Current Protection Register, TX_OCP_L (0Xa0), TX_OCP_H (0Xa1)
61
TX Conflict Threshold Register, Txconfthrsh (0X134)
61
TX Conflict Count Register, Txconfcnt (0Xaf)
61
TX Power Register, Tx_Power_L (0Xac), Tx_Power_H (0Xad)
61
TX Dead Time Register, Tx_Deadtime (0X9C)
61
TX Control Delay Register, Tx_Controldelay (0Xae)
62
Commonly Used Registers
62
2.1.13.1. Monitoring, Status, Interrupt, and Operating Mode Registers
62
2.1.13.2. Settings and Command Registers
62
3 Schematic Diagram
63
Figure 31. P9412 DEMO Board V1.3 Schematic
63
4 Bill of Materials
64
Table 1. Bill of Materials
64
5 Board Layout
66
Figure 32. Top and Top Silkscreen Layer
66
Figure 33. Inner1 GND Layer
67
Figure 34. Inner2 Power/Signal/Gnd Layer
68
Figure 35. Inner3 POWER/ GND Layer
69
Figure 36. Inner4 Power/Signal/Gnd Layer
70
Figure 37. Bottom Layer
71
Figure 38. FTDI Dongle for Programming the Firmware into P9412 MTP
72
FTDI Dongle
72
Figure 39. FTDI Dongle Schematic for Programming the Firmware into P9412 MTP and Reading Registers
73
6 Ordering Information
74
7 Revision History
74
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Renesas P9412 Layout Manual (22 pages)
Brand:
Renesas
| Category:
Receiver
| Size: 3.43 MB
Table of Contents
Table of Contents
1
Introduction
2
Figure 1. P9412 Block Diagram
2
Power Circuits
3
Figure 2. P9412 Power Circuits Hot Loop Current Paths Simplified Schematic Diagram
3
Figure 3. P9412 CSP Suggested Orientation
4
Power Schematic and Layout Examples
5
Figure 4. P9412 Power Section, CSP DEMO Board Schematic
5
Figure 5. P9412 Physical Layout from CSP Demo PCB (Top Layer)
6
Figure 6. P9412 Physical Layout from Demo PCB Second Layer (MID1)
7
Figure 7. P9412 Layout from Demo PCB Third Layer (MID2)
8
Figure 8. P9412 Layout from Demo PCB Fourth Layer (MID3)
8
Figure 9. P9412 Layout from Demo PCB Fifth Layer (MID4)
9
Figure 10. P9412 Layout from Demo PCB Sixth Layer (Bottom)
9
BST Capacitors
10
Figure 11. BST Capacitors Placement and Routing Example
10
LDO1P8 (V1P8_AP), LDO5P0 (V5P0_AP), and Communication Capacitors
11
Figure 12. LDO1P8, LDO5P0, V1P8_AP, V5P0_AP, and Communication Capacitors
11
Sensitive Circuits
12
Table 1. Minimum Trace Width Routing Guide
12
Tx Specific Circuits for Wattsharetm Technologies
13
Figure 13. P9412 Transmitter DEMOD Circuit and Q-Factor Measurement Schematic
13
Figure 14. P9412 Tx DEMOD Filter and Qmeasurement Layout Example
14
Figure 15. P9412 Optional External CPOUT Current Sense Schematic and Layout
15
Non-Sensitive Circuits
16
PCB Footprint Design
16
Figure 16. P9412 CSP Recommended PCB Footprint Design Dimensions
16
10. Thermal Considerations
17
Figure 17. Examples of Heat Flow Paths and Multiple Layer Interactions
17
11. Audible Noise Suppression
18
Appendix A. Full Reference Schematic and Placement Diagram
19
References
21
Revision History
21
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