Renesas P9412 Layout Manual
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Contents
1.
Introduction .................................................................................................................................................... 2
2.
Power Circuits ................................................................................................................................................ 3
3.
Power Schematic and Layout Examples ..................................................................................................... 5
4.
BST Capacitors ............................................................................................................................................ 10
5.
LDO1P8 (V1P8_AP), LDO5P0 (V5P0_AP), and Communication Capacitors .......................................... 11
6.
Sensitive Circuits ......................................................................................................................................... 12
7.
Tx Specific Circuits for WattshareTM Technologies ............................................................................... 13
8.
Non-Sensitive Circuits ................................................................................................................................ 16
9.
PCB Footprint Design ................................................................................................................................. 16
10. Thermal Considerations .............................................................................................................................. 17
11. Audible Noise Suppression ........................................................................................................................ 18
Appendix A. Full Reference Schematic and Placement Diagram ................................................................... 19
References............................................................................................................................................................ 21
Revision History .................................................................................................................................................. 21
Figures
Figure 1. P9412 Block Diagram ................................................................................................................................ 2
Figure 3. P9412 CSP Suggested Orientation ........................................................................................................... 4
Figure 4. P9412 Power Section, CSP DEMO Board Schematic .............................................................................. 5
Figure 5. P9412 Physical Layout from CSP Demo PCB (Top Layer) ...................................................................... 6
Figure 6. P9412 Physical Layout from Demo PCB Second Layer (MID1) ............................................................... 7
Figure 7. P9412 Layout from Demo PCB Third Layer (MID2) .................................................................................. 8
Figure 8. P9412 Layout from Demo PCB Fourth Layer (MID3) ............................................................................... 8
Figure 9. P9412 Layout from Demo PCB Fifth Layer (MID4) ................................................................................... 9
Figure 10. P9412 Layout from Demo PCB Sixth Layer (Bottom) ............................................................................. 9
Figure 11. BST Capacitors Placement and Routing Example ................................................................................10
Figure 14. P9412 Tx DEMOD Filter and Qmeasurement Layout Example ............................................................14
Figure 16. P9412 CSP Recommended PCB Footprint Design Dimensions ..........................................................16
Figure 17. Examples of Heat Flow Paths and Multiple Layer Interactions .............................................................17
Tables
Table 1. Minimum Trace Width Routing Guide.......................................................................................................12
Rev.1.0
Jul.14.20
P9412 PCB Layout Guide
Page 1

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Summary of Contents for Renesas P9412

  • Page 1: Table Of Contents

    Figures Figure 1. P9412 Block Diagram ..........................2 Figure 2. P9412 Power Circuits Hot Loop Current Paths Simplified Schematic Diagram ........3 Figure 3. P9412 CSP Suggested Orientation ......................4 Figure 4. P9412 Power Section, CSP DEMO Board Schematic ................5 Figure 5.
  • Page 2: Introduction

    There are three main categories of circuitry, Power Circuits, Sensitive Circuits, and Non-Sensitive Circuits. Key points for optimal layout: Route power connections wide and on the same side of the PCB as the P9412 (≥ 2.54 mm). Use parallel • planes for conductivity improvements.
  • Page 3: Power Circuits

    P9412 PCB Layout Guide Power Circuits The main power circuits of the P9412 device are the resonance tank (WPC Rx and Tx), the integrated synchronous bridge rectifier/inverter, the MLDO linear regulator (VOUT), and the Capacitor Divider. Secondary power circuits are the BST and COM/CM capacitors, LDO5P0 (or V5P0_AP), and LDO1P8 (or (V1P8_AP) regulators.
  • Page 4: Figure 3. P9412 Csp Suggested Orientation

    PCB has been determined and the power transfer coils connection points (LRTX) are established that the P9412 be placed onto the board as close to the center of the PCB as possible. After the P9412 is placed, the orientation should be decided based on facing the AC1 and AC2 side (J-row) toward the physical coil connectors.
  • Page 5: Power Schematic And Layout Examples

    Finally, place DC stability capacitor dividing capacitor C71 followed by Clamping Resistors (R70, R2) and TVS (D6) or Zener (D13) protection diodes. Placing the above listed parts in the listed order and close to the P9412 while allowing room for routing is critical for optimal performance. It is important to keep the area of the hot current loops that conduct AC currents to a minimum.
  • Page 6: Figure 5. P9412 Physical Layout From Csp Demo Pcb (Top Layer)

    P9412 PCB Layout Guide Figure 5. P9412 Physical Layout from CSP Demo PCB (Top Layer) These are the currents paths from the synchronous bridge rectifier/inverter to the VRECT capacitors / VOUT (C59, C20) to PGND (J-row) as well as the capacitor divider VOUT (C21, C47), CFLY, CPOUT to CPGND (A-row CPGND vias) to keep ripple voltages, GND bounce, potential EMI minimized.
  • Page 7: Figure 6. P9412 Physical Layout From Demo Pcb Second Layer (Mid1)

    (8 or more) for any layer transition. Effort should be made to keep the first PCB layer under the P9412 free from unnecessary connections and a solid GND plane is recommended. This plane will carry electrical current, mirror currents from power conductors, and heat from heat sources to be spread across the PCB.
  • Page 8: Figure 7. P9412 Layout From Demo Pcb Third Layer (Mid2)

    P9412 PCB Layout Guide Figure 7. P9412 Layout from Demo PCB Third Layer (MID2) Figure 8. P9412 Layout from Demo PCB Fourth Layer (MID3) Parallel conduction planes for VOUT, AC1, AC2, CPOUT, Vrect to PCLAMP and all GND; CPBST1, CPBST3, Signal routing layer.
  • Page 9: Figure 9. P9412 Layout From Demo Pcb Fifth Layer (Mid4)

    P9412 PCB Layout Guide Figure 9. P9412 Layout from Demo PCB Fifth Layer (MID4) Figure 10. P9412 Layout from Demo PCB Sixth Layer (Bottom) Parallel conduction planes for all GND plane for heat dissipation and parallel conduction (connect as many PGND, CPGND, and GND vias-in-pad to as many GND planes as possible).
  • Page 10: Bst Capacitors

    CPBST2 should be placed. In Figure 11, the BST capacitors (C24, C22, C9, C12, and C23) are placed adjacent to the P9412 while leaving room for the CPP, CPN, AC1, and AC2 nodes to be routed to Cfly and in from the resonance tank.
  • Page 11: Ldo1P8 (V1P8_Ap), Ldo5P0 (V5P0_Ap), And Communication Capacitors

    This capacitor must be located close to the P9412 and should be located close to pin F4. Optimal placement is directly next to the P9412 column 1 and requires a direct connection back to GND pins.
  • Page 12: Sensitive Circuits

    GND planes separation from the pin under the Vrect/VOUT hot loop to the VOUT connection to C20 or C21 (VOUT capacitors near PGND). The DEMOD components should be placed near the A1 pin/corner of the P9412 to provide adequate GND isolation from the Rectifier/Inverter and Capacitor Divider Hot Loops. A single GND plane shared by all PGND, CPGND, and GND pins is highly recommended to optimize electrical and thermal conduction and avoid potential GND loops that extent the hot loop area.
  • Page 13: Tx Specific Circuits For Wattsharetm Technologies

    Tx Specific Circuits for WattshareTM Technologies The main power circuits of the P9412 in Tx mode are the synchronous bridge inverter and the resonance tank (capacitive divider operates in Bypass mode and passes the applied voltage directly to VRECT). Secondary power circuits are the LDO1P8, LDO5P0 regulators and the slew rate control capacitors (CM1, CM2) which are used for Zero-Voltage Switching control capacitors in Tx mode (follow Rx mode placement guidance).
  • Page 14: Figure 14. P9412 Tx Demod Filter And Qmeasurement Layout Example

    DEMOD pin E2. This section of the DEMOD path can be exposed to high voltages, so it should be electrically isolated by at least 0.127mm (10mils) from all other connections. Figure 14. P9412 Tx DEMOD Filter and Qmeasurement Layout Example Rev.1.0 Page 14 Jul.14.20...
  • Page 15: Figure 15. P9412 Optional External Cpout Current Sense Schematic And Layout

    P9412 PCB Layout Guide Figure 15. P9412 Optional External CPOUT Current Sense Schematic and Layout Rev.1.0 Page 15 Jul.14.20...
  • Page 16: Non-Sensitive Circuits

    PCB Footprint Design The P9412 package is a fine pitch CSP device and the PCB footprint is an important part of production assembly yields. Improper footprint design can lead to solder shorts or open circuits. Poor PCB footprint design can also cause the performance to be degraded by limiting the robustness and diameter of the pin-to-board connections.
  • Page 17: 10. Thermal Considerations

    P9412 PCB Layout Guide 10. Thermal Considerations The heat or thermal management of the P9412 PCB design is critical to performance and from the thermal perspective it is recommended to route the main power connections as wide as possible when connecting to the device and use the outer layer of the PCB for these connections.
  • Page 18: 11. Audible Noise Suppression

    For any additional questions, please refer them to your local Renesas Field Applications Engineer or Marketing Department and they will be addressed as soon as possible.
  • Page 19: Appendix A. Full Reference Schematic And Placement Diagram

    P9412 PCB Layout Guide Appendix A. Full Reference Schematic and Placement Diagram Rev.1.0 Page 19 Jul.14.20...
  • Page 20 P9412 PCB Layout Guide Rev.1.0 Page 20 Jul.14.20...
  • Page 21: References

    P9412 PCB Layout Guide References Spataro, Vincent. Counting squares: A method to quickly estimate PWB trace resistance. EDN Network. 2013 • April 12. Web. 2016 June 3 Revision History Revision Date Description Jul.14.20 Initial release. Rev.1.0 Page 21 Jul.14.20...
  • Page 22 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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