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3.5.1 JP27, JP29 (on-board SRAM bus configuration)
These select the on-board SRAM bus size.
(1) JP27 (SRAM_MODE1)
JP27
1-2 (32)
32-bit bus.
2-3 (16)
16-bit bus.
Open
This setting is prohibited because A19 pin of lower on-board SRAM enters high-impedance state.
(2) JP29 (SRAM_MODE2)
JP29
1-2 (32)
32-bit bus.
2-3 (16)
16-bit bus.
Open
This setting is prohibited because CE pin of higher on-board SRAM enters high-impedance state.
3.5.2 JP2 (INTPZ8 interrupt signal)
This selects the INTPZ8 (P10) signal to be input to the PFESiP/V850EP1.
JP2
1-2 (FPGA)
Connects P10 of on-board FPGA to INTPZ8 (P10) pin.
2-3 (FROM)
Connects RY/BY signal of flash ROM to INTPZ8 (P10) pin.
Select this if RY/BY signal is required when writing to flash ROM.
Open
This setting is prohibited because INTPZ8 (P10) pin enters high-impedance state.
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CHAPTER 3
Positions
Figure 1-1 (Appearance) F-4, F-5
The settings of JP27 and JP29 must be the same.
On-Board SRAM Bus Size Switching (Addr)
Connects A21 signal to A19 pin of lower on-board SRAM.
Connects A1 signal to A19 pin of lower on-board SRAM.
On-Board SRAM Bus Size Switching (CS)
Connects CS signal to CE pin of higher on-board SRAM.
Fixes CE pin of higher on-board SRAM to "H".
Position
Figure 1-1 (Appearance) C-3
INTPZ8 (P10) Source Switching
User's Manual
SWITCH SETTINGS
A19350EJ1V1UM
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