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Chapter 6: Solving Problems
If the analyzer won't trigger
If the analyzer won't trigger
Instruction fetches from internal 6833x resources normally aren't visible to the
analyzer. You can force them to be visible by enabling show cycles. The SIM
register MCR allows you to set show cycles. To obtain the show cycles feature of
the processor, set the two least-significant bits in the third byte of register
SIM_MCR to "11". For example:
R>reg emsim_mcr=63cf
R>rst -m
M>
If the analyzer triggers on a program address
when it should not
Check to see if the analyzer is triggering on an instruction prefetch. The analyzer
cannot distinguish between prefetch and execution because the processor does not
provide that information. Usually your actual trigger address is within four words
of the address where trigger is occurring.
Try to pad the program code with NOP instructions to move the trigger address
away from the other code so that it won't be prefetched until it is time to trigger.
You may be able to insert a write instruction to a meaningless variable in your code
immediately following the trigger address. Then you can trigger on a write to the
address of the variable. Write transactions never appear in instruction prefetches.
110
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