Chapter 4: Connecting the Emulator to a Target System
processor does not grant the bus until it is idle so bus ownership changes as soon as
the BG signal is asserted. The alternate master asserts BGACK to claim the bus
before deasserting BR.
If the bus is granted by the processor but is not being returned, check the bus
arbitration signals BR, BG, and BGACK. If the bus is never released, the alternate
bus master may be stuck in the middle of a cycle. Check the cycle strobes AS,
DSACK, and BERR. These strobes do not have to be asserted during alternate
master accesses, but if AS is shown to the processor, it will generate memory
control signals and may even provide DSACK for the alternate master bus cycle.
If some cycles are shown in the trace list, but no cycles are occurring now, the
processor executed some cycles before getting stuck in a DMA cycle. Examine the
bus arbitration signals and cycle strobes around where the target system gets stuck.
Use the same techniques to set up a trigger as were described for measuring a bus
cycle that stops before it is complete.
If bus cycles are occurring, then the "g>" prompt indicates that a high percentage of
the bus activity is by alternate bus masters.
Interpreting the trace list
In some cases, a problem caused by an errant bus cycle may not show up until
many cycles later. The emulation-bus analyzer must be used to track back thru the
sequence of events to the faulty bus cycle. Data problems often give this delayed
appearance, but there may be other causes.
If the "h>" prompt is shown, indicating a double bus fault, and if there are only four
states in the tracelist, this indicates a problem with fetching of the initial vectors.
h>tl
Line
addr,H
6833x Mnemonic
-----
------
------------------------------------------
0
000000
$0000
1
000002
$0000
2
000004
$0BAD
3
000006
$ADDR
4
h>
The first four cycles in the trace list are the initial stack pointer and the initial
program counter. The initial program counter must be even or the processor will
Plugging The Emulator Into A Target System
data word rd (ds16)
data word rd (ds16)
data word rd (ds16)
data word rd (ds16)
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