HP 64782 Series Manual page 150

Chapter 9: Specifications and Characteristics
HP 64782 AC Timing Specifications
Num Characteristic
21 R/W Asserted to AS, CS Asserted
22 R/W Low to DS, CS Asserted (Write)
23 Clock High to Data Out Valid
24 Data Out Valid to Negating Edge of
AS, CS (Fast Write Cycle)
25 DS, CS Negated to Data Out Invalid
(Data Out Hold)
26 Data Out Valid to DS, CS Asserted
(Write)
27 Data In Valid to Clock Low (Data
Setup)
27A Late BERR, HALT Asserted to Clock
Low (Setup Time)
28 AS, DS Negated to DSACK[1:0] ,
BERR, HALT, AVEC Negated
29 DS, CS Negated to Data In Invalid
(Data In Hold)
29A DS, CS Negated to Data In High
Impedance
30 CLKOUT Low to Data In Invalid (Fast
Cycle Hold)
30A CLKOUT Low to Data In High
Impedance
138
HP 64782 — AC TIMING SPECIFICATIONS
= 5.0 Vdc ±10%, V
( and V
V DD
DDSYN
= 0 Vdc)
SS
16.78 MHz
Min Max Min
15 — 10
70 — 54
— 27 —
15 — 10
15 — 10
15 — 10
10 — 10
25 — 20
0 80 0
0 — 0
— 55 —
13 — 8
— 88 —
20.97 MHz
Unit
Max
— ns
— ns
21 ns
— ns
— ns
— ns
— ns
— ns
60 ns
— ns
48 ns
— ns
70 ns