Board Modifications; Mechanical Specifications; Environmental Requirements - Lattice Semiconductor ispMACH 4256V User Manual

Breakout board evaluation kit
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Table 11. USB Interface Reference
Reference Designator
Part Number
Manufacturer
Web Site
External Oscillator
A 5 MHz external oscillator is used to provide clock input to the ispMACH 4256V chip.
Table 12. External Oscillator Reference
Reference Designator
Part Number
Manufacturer
Web Site

Board Modifications

This section describes modifications to the board to change or add functionality.
Bypassing the USB Programming Interface
The USB programming interface circuit (section 6.2.8 USB Programming and Debug Interface) may be optionally
bypassed by removing the 0 ohm resistors: R3, R4, R7, and R9 (See Schematic Sheet 2 of 4,
matics). Header landing J1 provides JTAG signal access for jumper wires or a 1 x 8 pin header.
Applying External Power
The Breakout Board is powered by the circuit of Schematic Sheet 2 of 4 based on the 5 V USB power source. You
may disconnect this power source by removing the 0 ohm resistors: R47 (VCCO 3.3 V, Bank 0), R48 (VCCO 3.3 V,
Bank 1), and R53 (VCC 3.3 V, Core). Power connections are available from the expansion header landing, J6,
Schematic Sheet 3 of 4.
Measuring Bank and Core Voltages
Test points (TP1, TP2, and TP3) provide access to bank VCCO and VCC core power supplies of the ispMACH
4256V CPLD. 0 Ohm resistors: R47 (VCCO 3.3 V, Bank 0), R48 (VCCO 3.3 V, Bank 1), and R53 (VCC 3.3 V, Core)
can be removed to add a current meter inline or add a resistor shunt to measure voltage across.

Mechanical Specifications

Dimensions: 3 in. [L] x 3 in. [W] x 1/2 in. [H]

Environmental Requirements

The evaluation board must be stored between -40° C and 100° C. The recommended operating temperature is
between 0° C and 90° C.
The board can be damaged without proper anti-static handling.
ispMACH 4256V Breakout Board Evaluation Kit
Item
U2
FT2232HL
Future Technology Devices International (FTDI)
www.ftdichip.com
Item
X5
SIT8918AE-13-33E-5.000000G
SiTIME (SIT)
www.sitime.com
15
Description
Description
Appendix A. Sche-

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