Lattice Semiconductor ispMACH 4256V User Manual page 7

Breakout board evaluation kit
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Figure 3. ispMACH 4256V Breakout Board Block Diagram
A/Mini-B
USB Cable
Table 1 describes the components on the board and the interfaces it supports.
Table 1. Breakout Board Components and Interfaces
Component/Interface
Circuits
USB Controller
USB Mini-B
Socket
Components
LC4256V
SiTIME5.00000M
Interfaces
LED Array
Four 2x20 header landings
1 x 8 header landing
4 x 15 prototype area
Subsystems
This section describes the principle subsystems for the ispMACH 4256V Breakout Board in alphabetical order.
Clock Sources
All clocks for the counter demonstration design originates from an external 5 MHz oscillator connected to Pin 128
of ispMACH 4256V chip. You may use an expansion header landing to drive a CPLD input with an alternate clock
source. To drive Pin 128 from header J4, disconnect X5 from the circuit by removing R23.
Expansion Header Landings
The expansion header landings provide access to user GPIOs, primary inputs, clocks, and Bank 0/1 VCCO pins of
the ispMACH 4256V. The remaining pins serve as power supplies for external connections. Each landing is config-
ured as one 2 x 20 100 mil.
Table 2. Expansion Connector Reference
2 x 20 Header
Landing (J3)
2 x 20 Header
Landing (J4)
5 MHz
Oscillator
Programming
USB Mini B
USB
Controller
Socket
Type
Schematic Reference
Circuit
U2: FT2232H
I/O
J1:USB_MINI_B
CPLD
U4: LC4256V-5TN144C
X5: SIT8918AE-13-33E-
Oscillator
5.000000G
Output
D8-D1
J3: header_2x20
J4: header_2x20
I/O
J5: header_2x20
J6: header_2x20
I/O
J1: header_1x8
J9
Item
Reference Designators
Part Number
ispMACH 4256V Breakout Board Evaluation Kit
20 GPIO
35 GPIO
ispMACH4256V-5T
N144C
JTAG
USB-to-JTAG interface and dual USB UART/FIFO IC
Programming and debug interface
256-macrocell CPLD packaged in a 20 mm x 20
mm, 144-pin TQFP
SiTIME 5 MHz external SMD oscillator
Red LEDs
User-definable I/O
Optional JTAG interface
Prototype area 100mil centered holes
Description
J3, J4, J5, J6
header_2x20
7
40 GPIO
2 x 20 Header
Landing (J5)
15 GPIO
2 x 20 Header
Landing (J6)
8
1 x 8 JTAG Header
Landing (J1)
8
LED
Array
Description

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