Pcie Ip Prototyping Kit Directory Structure - Synopsys DesignWare 826-0 Installation Manual

PCIe IP Prototyping Kit Installation Guide
2.5

PCIe IP Prototyping Kit Directory Structure

After you have unpacked the PCIe IP Prototyping Kit environment, the files are included in the following
directory structure. See
For details on how to create a workspace, configure, synthesize, simulate, using coreConsultant, refer to the
DesignWare PCIe IP Prototyping Kit User Guide.
Each workspace you create in coreConsultant will have a similar folder structure. The folder
Note Note Note Note
content is created after you create a coreConsultant workspace.
Figure 2-1 Prototyping Kit Directory Structure
Table 2-2 Prototyping Kit Directory Structure Description
Directory/Sub-directory
./
./dwipk_pcie/<version>/<workspace>
./cores/
./doc/
./syn/
./bin/
./src/
5.60a
March 2020
Table 2-2 for the folder content description.
./
dw_dwipk_pcie/<version>/
cores
doc
syn
bin
src
sim
software
phy
Description
Top level directory.
Main makefile, used to launch all FPGA synthesis flow.
Environment configuration makefile (config.mk), used to configure all the environment
needed tools and licenses, used on the flow.
Configuration files directory. Applies to user configurable blocks, such as the
DWC_pcie_ctl IP.
Documentation directory.
FPGA synthesis directory with a fully functional pre-built HW bitfile.
Workspace environment scripts directory (for coreConsultant handling).
Top level source files directory. It also includes encrypted DW IPs.
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<workspace>
Setting Up Software Environment
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