Synopsys DesignWare 826-0 Installation Manual
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Synopsys DesignWare 826-0 Installation Manual

Pcie ip prototyping kit
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DesignWare
Installation Guide
®
PCIe IP Prototyping Kit
dw_ipk_dwipk_pcie –
Product
Codes: E826-0
March 2020
E825-0
C368-0
C369-0
C046-0
E025-0
E026-0
E027-0
E827-0
E828-0
5.60a

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  • Page 1 ® DesignWare PCIe IP Prototyping Kit Installation Guide dw_ipk_dwipk_pcie – Product Codes: E826-0 E825-0 C368-0 C369-0 C046-0 E025-0 E026-0 E027-0 E827-0 E828-0 5.60a March 2020...
  • Page 2 © 2020 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

  • Page 3: Table Of Contents

    A.4 ARC HSDK Development Kit Board LEDs ........... 54 5.60a Synopsys, Inc. SolvNetPlus...
  • Page 4 Contents PCIe IP Prototyping Kit Installation Guide Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...

  • Page 5: Setting Up Hardware Components

    Before setting up the hardware components, make sure you read the DesignWare PCIe IP Note Note Note Note Prototyping Kit Release Notes. This document is divided in the following sections: “Contents of PCIe IP Prototyping Kit” on page ■ “Hardware Setup” on page ■ 5.60a SolvNetPlus Synopsys, Inc. March 2020 DesignWare...

  • Page 6: Product Codes

    DesignWare PCIe Gen4 Endpoint Controller on HAPS-80, E16 PHY, PCIe connection for PC E825-0 DesignWare PCIe Gen5 Root Complex Controller on HAPS-80, E32 PHY, AXI tunnel to ARC HS E828-0 DesignWare PCIe Gen5 Endpoint Controller on HAPS-80, E32 PHY, with PCIe connection to PC E827-0 Synopsys, Inc. SolvNetPlus 5.60a DesignWare...

  • Page 7: Contents Of Pcie Ip Prototyping Kit

    Figure 1-1 shows PCIe Root Complex IP Prototyping Kit recommended components for the kits using Synopsys PHY on HAPS-80 Figure 1-1 PCIe Root Complex IP Prototyping Kit Components with Synopsys PHY on HAPS-80 5.60a Synopsys, Inc. SolvNetPlus March 2020...
  • Page 8 Setting Up Hardware Components PCIe IP Prototyping Kit Installation Guide The Synopsys PCIe PHY can be a Synopsys C10 PHY, a Synopsys E16 PHY or a E32 PHY Note Note Note Note board. Table 1-2 for more details. Figure 1-2 shows the PCIe Endpoint IP Prototyping Kit recommended components for the kits using Synopsys PHY on HAPS-80.
  • Page 9 Figure 1-3 PCIe Root Complex IP Prototyping Kit Components with Xilinx PHY on HAPS-80 Figure 1-4 shows the PCIe Endpoint IP Prototyping Kit recommended components for the kits using the Xilinx PHY on HAPS-80. 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...
  • Page 10 Setting Up Hardware Components PCIe IP Prototyping Kit Installation Guide Figure 1-4 PCIe Endpoint IP Prototyping Kit Components with Xilinx PHY on HAPS-80 HAPS-80 RISER1_MGB PCIE-8_PDL_MGB Card PCIe x8 Extender Cable Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...
  • Page 11 PCIe IP Prototyping Kit Installation Guide Setting Up Hardware Components Figure 1-5 PCIe Endpoint IP Prototyping Kit Components with E32 PHY on HAPS-80 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...
  • Page 12 DesignWare PCIe Gen4 Root Complex Controller on HAPS-80, E16 PHY, AXI tunnel to ARC SDP (E826-0) HW0352-000 HAPS-80 S26 (-2) High-Performance ASIC Prototyping System HAPS-80 DWC_PHY_E16_P PHY Board Synopsys E16 PHY Board (PCIe Gen4 PHY) CIe_Gen4 8KH2-0723-0250 PCIe x8 Twin Axial Cable Assembly or PCIe x8 extender card Extender...
  • Page 13 DesignWare PCIe Gen4 Endpoint Controller on HAPS-80, E16 PHY, PCIe connection for PC (E825-0) HW0352-000 HAPS-80 S26 (-2) High-Performance ASIC Prototyping System HAPS-80 DWC_PHY_E16_P PHY Board Synopsys E16 PHY Board (PCIe Gen4 PHY) CIe_Gen4 8KH2-0723-0250 PCIe x8 Twin Axial Cable Assembly or PCIe x8 extender card Extender...
  • Page 14 DesignWare PCIe Gen5 Root Complex Controller on HAPS-80, E32 PHY, AXI tunnel to ARC HS (E828-0) HW0352-000 HAPS-80 S26 (-2) High Performance ASIC Prototyping System (HAPS-80) DWC_PHY_E32_P PHY Board Synopsys E32 PHY Board (PCIe Gen5 PHY) CIe_Gen5 HW0469-000 ARC HSDK DW ARC HSDK Development Kit 3052113...
  • Page 15 Motherboard or PTC card. The PCIE-4 MGB Kit has an embedded PCIe bridge chip, that influences test results. Note Note Note Note To power the PCIe Backplane you need an ATX power supply. 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...

  • Page 16: Hardware Setup

    If you are using the IP Prototyping Kit with the Xilinx PHY, follow the steps to 7. ■ Note Note Note Note If you are using the IP Prototyping Kit with the Synopsys PHY (E16, C10 or E32 PHY), ■ jump to step 8. Synopsys, Inc. SolvNetPlus 5.60a DesignWare...
  • Page 17 Detail of the HAPS-80 MGB Shelves Remove the MGB Shelves from the HAPS-80 and insert the RISER1_MGB card in the MGB Shelves, as shown in Figure 1-9. Figure 1-9 Detail of the RISER1_MGB and HAPS-80 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...
  • Page 18 PCIE-8 paddle board (See Figure 1-7). Connect the Synopsys PCIe PHY Board to the HAPS-80 board. If you're using a C10 PHY, use HT3 ports J5-J10 on the HAPS-80 and ports P1-P6 on the C10 PHY to mechanically connect the boards.

  • Page 19: Setting Up Pcie Root Complex Ip Prototyping Kits

    Setting Up PCIe Root Complex IP Prototyping Kits This section provides instructions for setting up a PCIe Root Complex IP Prototyping Kit hardware, using the Xilinx, or a Synopsys PCIe PHY board. To power the PCIe Backplane you need an ATX power supply.
  • Page 20 Flip the PCIe Backplane board over the HAPS-80 board and align the Paddle board with the MGB Brackets, see Figure 1-13 on page 22. The Synopsys PCIe PHY can be a Synopsys C10, E16 or E32 PHY board. Synopsys, Inc. SolvNetPlus 5.60a...
  • Page 21 During the power-up sequence, the supervision LEDs (RESET, READY, ALERT, and PWR) change color. After a successful power-up sequence, all LEDs must be green (see Appendix A, “Status LEDs”, section A.2). The LED marked UDONE indicates if the FPGA is configured. 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...
  • Page 22 HAPS-80 FPGA build into the SD card, see chapter “Loading HAPS-80 FPGA Build” in the DesignWare PCIe IP Prototyping Kit User Guide. Figure 1-13 PCIe Root Complex IP Prototyping Kit Setup Using the Xilinx PHY Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...
  • Page 23 Figure 1-14 PCIe Root Complex IP Prototyping Kit Setup Using a C10 PHY Board and HAPS-80 If you are using the Synopsys PHY board, connect the Synopsys PHY board to the PCIe Root Complex slot of the PCIe Backplane board.
  • Page 24 Setting Up Hardware Components PCIe IP Prototyping Kit Installation Guide Figure 1-15 PCIe Root Complex IP Prototyping Kit using the E16 PHY Board and HAPS-80 Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...
  • Page 25 Sequence”). The LED marked UDONE indicates if the FPGA is configured. Power up the ARC HSDK system board. After power-up the ARC HSDK the PWR LED must be green and also LED 1. LEDs 2-4 must be turned OFF. 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...
  • Page 26 Setting Up Hardware Components PCIe IP Prototyping Kit Installation Guide Figure 1-16 PCIe Root Complex IP Prototyping Kit using the E32 PHY board and HAPS-80 Figure 1-17 ARC HSDK Development Kit Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...

  • Page 27: Setting Up Pcie Endpoint Ip Prototyping Kits

    If you are using a prototyping kit with the Xilinx PHY, the PCIe extender cable is connected to the ❑ PCIE-8 paddle board. If you are using a prototyping kit with the Synopsys PHY, the PCIe extender cable is connected ❑ directly to the Synopsys PHY.
  • Page 28 Setting Up Hardware Components PCIe IP Prototyping Kit Installation Guide Figure 1-18 PCIe Gen3 Endpoint IP Prototyping Kit Setup Using a Synopsys C10 PHY Figure 1-19 illustrates the assembled PCIe Endpoint IP Prototyping Kit using the E16 PHY. Figure 1-20 illustrates the assembled PCIe Endpoint IP Prototyping Kit using the Xilinx PHY.
  • Page 29 To setup the HAPS-80 board, for the PCIe Endpoint IP Prototyping Kit using Xilinx PHY, refer to “Setting Up HAPS-80” on page Figure 1-20 PCIe Endpoint IP Prototyping Kit Setup Using the Xilinx PHY 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...
  • Page 30 Sequence”). The LED marked UDONE indicates if the FPGA is configured. Power up the computer on which you are running the system. The HAPS-80 board LED1 turns green to indicate the PCIe link connection (see “Appendix A.2, “HAPS-80 Power-Up Sequence”). Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...
  • Page 31 PCIe IP Prototyping Kit Installation Guide Setting Up Hardware Components Figure 1-22 Connection between HAPS-80 and E32 PHY 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...
  • Page 32 Setting Up Hardware Components PCIe IP Prototyping Kit Installation Guide Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...

  • Page 33: Setting Up Software Environment

    This chapter provides the required steps for setting up your environment to use a prototyping kit. The following topics are described: “Licensing and Tool Requirements” ■ “Setting License File Environment Variable” ■ “Installing dw_ipk_dwipk_pcie” ■ “Creating a Workspace” ■ “PCIe IP Prototyping Kit Directory Structure” on page ■ 5.60a SolvNetPlus Synopsys, Inc. March 2020 DesignWare...

  • Page 34: Licensing And Tool Requirements

    Tclsh is a shell-like application that reads and evaluates Tcl commands from a standard input or from a file. Configuring and Rebuilding FPGA Image CoreConsultant 2019.06-SP2 The Synopsys coreConsultant tool facilitates design reuse by providing reliable, error-free design configuration and high-quality synthesis of reusable (coreTools) cores. VCS (VCS VCSi) 2018.09-SP2...
  • Page 35 The DW_axi_gs is used to reply to requests from the PCIe Axi bridge. Verification IP (VIP) P-2019.09 VIP testbenches that comply with the SystemVerilog Universal Verification Methodology (UVM). a. Make sure to install all packages of HAPS ProtoCompiler (ConfPro and ProtoCompiler Runtime) 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...

  • Page 36: Setting License File Environment Variable

    % lmstat -c $SNPSLMD_LICENSE_FILE -f <LICENSE_NAME> Use these commands to check the license setup for all of your component’s required licenses Note Note Note Note as described in Table 2-1 on page 34. Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...

  • Page 37: Installing Dw_Ipk_Dwipk_Pcie

    For more details about install release package, enter the following command: % ./dw_ipk_dwipk_pcie_<version>.run –-help To start the self-extracting process, enter the following command: % ./dw_ipk_dwipk_pcie_<version>.run --dir <installation_folder> When prompted, enter the Project ID that you specified at the time of purchase. 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...

  • Page 38: Creating A Workspace

    This creates the RTL for the default configuration and populates the product documentation (in <workspace>/doc). You can create several workspaces so that you can experiment with different design Note Note Note Note alternatives. Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...

  • Page 39: Pcie Ip Prototyping Kit Directory Structure

    Documentation directory. ./syn/ FPGA synthesis directory with a fully functional pre-built HW bitfile. ./bin/ Workspace environment scripts directory (for coreConsultant handling). ./src/ Top level source files directory. It also includes encrypted DW IPs. 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...
  • Page 40 Software drivers and files directory with a fully functional pre-built Linux image. ./phy/ Xilinx PHY files After you set up the PCIe IP Prototyping Kit environment, continue to “Installing Software Note Note Note Note Drivers” on page 41. Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...

  • Page 41: Installing Software Drivers

    ARC SDP or ARC HSDK, for running the PCIe Initialization Tool and PCIe Test Tool. It contains the following topics: “Connecting to ARC SDP/ARC HSDK” on page ■ “Starting ARC SDP/ARC HSDK” on page ■ 5.60a SolvNetPlus Synopsys, Inc. March 2020 DesignWare...

  • Page 42: Connecting To Arc Sdp/Arc Hsdk

    USB Serial Port number used by the system. Open the Windows Device Manager. In either the Start Search or Run box, enter the following command: mmc devmgmt.msc Expand the “Ports (COM & LPT)” list. Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...
  • Page 43 In the PuTTY configuration window, use the following configuration parameters. Before typing the configuration parameters, change the connection type to “Serial”. Serial line: Use the USB Serial Port number (COM4 is used in this example) ❑ Speed: 115200 ❑ 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...
  • Page 44 Save the configuration parameters using the Sessions feature. Type a session name (for example, “ARC” as shown in Figure 3-2) and click Save. To start a session, click Open. If prompted for a username use the following: Note Note Note Note Username: root Password: root Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...

  • Page 45: Installing The Adept Driver

    Note Note of the Digilent Adept tool from the Digilent web site http://www.digilentinc.com. Download the latest version of the Adept System and install the Digilent Adept tool using the installation instructions from Digilent. 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...

  • Page 46: Starting Arc Sdp/Arc Hsdk

    DesignWare PCIe Software User Guide. Rebuilding the Linux environment ■ Installing the software drivers ■ For more information about bring up and software test, refer to the DesignWare PCIe IPK User Guide, “Testing the System” chapter. Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...

  • Page 47: Status Leds

    This chapter provides information about the PCIe IP Prototyping Kit LEDs. The following topics are described: “HAPS-80 Supervision LEDs” on page ■ “HAPS-80 Power-Up Sequence” on page ■ “ARC SDP Board LEDs” on page ■ “ARC HSDK Development Kit Board LEDs” on page ■ 5.60a SolvNetPlus Synopsys, Inc. March 2020 DesignWare...

  • Page 48: Haps-80 Supervision Leds

    HAPS-80 Supervision LED State and Description Color Description SDCARD SD Card is available Flash configuration in progress No SD Card or no access RESET Reset is released for all FPGAs Reset is active Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...
  • Page 49 FPGA configuration in progress No alert FPGA temperature over limit FPGA power off (Power) FPGA power OK FPGA power failure SVDONE Supervisor is configured UDONE FPGA is configured MDONE Supervisor (CLPD) is configured 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...

  • Page 50: Haps-80 Power-Up Sequence

    Error Stop Power - Check Error Stop Slave Systems Version - Check Error Stop Startup Project - Load Continue Startup Project - Loaded Successfully Error Continue Control Module – Power On ERROR Stop Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...
  • Page 51 Supervisor Firmware – Check and Load OK Error Stop Power Modules – Check Error Stop Slave Systems Version – Check Error Stop Startup Project – Load Continue Startup Project – Loaded Successfully Error Continue 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...

  • Page 52: Arc Sdp Board Leds

    Indicates the status of the AXI tunnel to the ARC CPU Card. Failure. Check the ARC CPU card connection to the ARC SDP board. TUNNEL1 Indicates the status of the AXI tunnel to the HAPS system. Failure. Check the HT3 connection cable. Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...
  • Page 53 SWPORTB_DR[20] SWPORTB_DR[18] SWPORTB_DR[23] SWPORTB_DR[19] SWPORTB_DR[31:24] Controls the lower seven-segment display. A segment of the display is ON when its control bit is set to 1. SWPORTB_DR[24] SWPORTB_DR[29] SWPORTB_DR[25] SWPORTB_DR[30] SWPORTB_DR[28] SWPORTB_DR[26] SWPORTB_DR[31] SWPORTB_DR[27] 5.60a Synopsys, Inc. SolvNetPlus March 2020 DesignWare...

  • Page 54: Arc Hsdk Development Kit Board Leds

    ARC HSDK on a HAPS system through the HapsTrak 3 connectors. blue The ARC HSDK is in Peripheral MODE. This mode is currently not available. green Indicates that the power supplies for the ARC HSDK are OK. Synopsys, Inc. SolvNetPlus 5.60a DesignWare March 2020...

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