Synopsys DesignWare ARC AXC003 Manuals

Manuals and User Guides for Synopsys DesignWare ARC AXC003. We have 1 Synopsys DesignWare ARC AXC003 manual available for free PDF download: User Manual

Synopsys DesignWare ARC AXC003 User Manual (145 pages)

Brand: Synopsys | Category: Computer Hardware | Size: 3 MB

Table of Contents
3
Contents
3
List of Figures
7
List of Tables
9
Package Contents
10
Designware ARC AXS103 Software Development Platform
10
Designware ARC AXC003 CPU Card
10
Designware ARC AXC003 CPU Card (Standalone)
11
Getting Started
12
Mounting the CPU Card
12
Performing a Self-Test
12
Location of the ARC SDP Mainboard Power Supply and Power Switch
13
ARC SDP Mainboard Status Leds after Power-On
13
AXC003 CPU Card Power-Control Leds after Power-On
14
Default Board Settings
15
Default Jumper Settings on the AXC003 CPU Card
15
Default Boot-Mode Settings on the ARC SDP Mainboard
16
Default Settings of the DIP Switches on the ARC SDP Mainboard
16
CPU Core Selection
17
Supported CPU Cores
17
Core Selection
17
Arc Hs36 Cpu
18
Arc Hs34 Cpu
18
ARC HS38 Core 0
18
ARC HS38 Core 1
18
Self-Tests
19
Self-Test Overview
19
Table 1 Self-Test Start Buttons
20
Location of the CPU Leds on the ARC SDP Mainboard
21
Location of the Led121X on the AXC003 CPU Card
21
Table 2 Characters on the Seven-Segment Display During the Self-Test
21
Executing the Self-Test of the ARC HS36 Core
22
Location of the ARC SDP Mainboard's Power Supply and Power Switch
22
Location of the CPU Start Button SW2504 for the ARC HS36 Core
22
Executing the Self-Test of the ARC Hs38X2 Core
23
ARC HS36 Self-Test
23
Location of the RESET Button on the ARC SDP Mainboard
23
Location of the ARC SDP Mainboard's Power Supply and Power Switch
24
Location of the CPU Start Button SW2504 for the ARC Hs38X2 Core
24
Restoring the Self-Tests in the SPI Flash
25
Screen-Shot of ARC Hs38X2 Self-Test
25
Location of the RESET Button on the ARC SDP Mainboard
25
Hardware Functional Description
27
Board Overview
27
Hardware Block Diagram (HS36)
28
Hardware Block Diagram (Hs38X2)
29
Board Interface Overview
30
Power Supply Connector
30
Hapstrak II Connectors (Bottom)
30
Hapstrak II Connectors (Top)
31
Mictor Connectors
31
Jumpers
31
Table 3 Jumper Functionality
31
Leds
32
Location of the Power Control Leds on the AXC003 CPU Card
32
Location of the User Leds on the AXC003 CPU Card
32
Pushbutton
33
Table 4 LED Control Bits
33
Seven-Segment Displays
34
Location of the Pushbutton on the AXC003 CPU Card
34
AXC003 Processor FPGA Overview
35
Main Features of the ARC Cores
35
Table 5 Control Bits of the Seven-Segment Displays
35
Table 6 Main Features of the ARC Cores
36
Pae
37
AXC003 Memory Map
37
I/O Coherency
38
AXC003 I/O Coherency Architecture
38
Interrupts
39
I/O Coherency and PAE
39
HS36 Interrupt Architecture
41
Hs38X2 Interrupt Architecture
42
Table 7 Interrupt Mapping for ARC HS36
43
Table 8 Interrupt Mapping for ARC HS38
44
Table 9 Mainboard ICTL Interrupt Mapping
45
Clock
46
Clock Architecture
47
Reset
48
Location of the RESET Button on the ARC SDP Mainboard
48
Table 10 Clock Frequencies
48
Debug
49
JTAG Daisy-Chain
49
Table 11 JTAG ID Codes
49
Control Registers
50
Table 12 Control Register Memory Map
50
GPIO Registers
52
Table 13 GPIO Register Memory Map
52
Table 14 GPIO Port a Output Register Bit Function (SWPORTA_DR)
52
Table 15 GPIO Port a Input Register Function (EXT_PORTA)
53
Table 16 GPIO Port B Output Register Function (SWPORTB_DR)
54
DIP Switches for FPGA Image Selection
55
Table 17 GPIO Port B Input Register Function (EXT_PORTB)
55
ARC HS34 Emulation
56
Table 18 Memory Mapping for ARC HS36
56
Memories on the AXC003 CPU Card
57
Table 19 Memory Mapping for HS34 Emulation
57
Power Supply
58
Table 20 Pinout of the Power-Supply Connector
58
Audio Support
59
Usage of ARC SDP Mainboard Resources
59
Usage of the Mainboard DIP Switches
59
Pinout of the Power Supply Connector (Bottom View)
59
Location of the Power Control Leds on the AXC003 CPU Card
59
Table 21 ARC Core Boot Configuration (Mainboard DIP Switch SW2501)
60
Table 22 Multicore Configuration (Mainboard DIP Switch SW2503)
61
Usage of the Mainboard Pushbuttons
62
Function and Default Settings of the DIP Switches on the ARC SDP Mainboard
62
Usage of the Mainboard Leds
63
Location of the CPU Start Buttons on the ARC SDP Mainboard
63
Table 23 Usage of the CPU Start Buttons of the ARC SDP Mainboard
63
Location of the CPU Leds on the ARC SDP Mainboard
64
Table 24 Control Bits of the CPU Leds on the ARC SDP Mainboard
64
System Memory Map
65
System Memory Map after a Reset
65
System Memory Map after Pre-Bootloader Execution
65
Table 25 ARC CPU Memory Map after Pre-Bootloader Execution
65
Controlling the Memory Map
67
Setting up the AXI Masters on the AXC003 CPU Card
67
Table 26 AXI Tunnel Memory Map after Pre-Bootloader Execution (ARC HS34 / HS36)
67
Table 27 AXI Tunnel Memory Map after Pre-Bootloader Execution (ARC HS38)
67
Setting up the AXI Masters on the ARC SDP Mainboard
68
Table 28 AXC003 CPU Card Target Slaves
68
Table 29 ARC SDP Mainboard Target Slaves
68
Example Register Settings for the Default Memory Map
69
Table 30 ARC CPU Memory Map Pre-Boot Programming on the AXC003 CPU Card
69
Table 31 Memory Map Pre-Boot Programming for All Masters on the ARC SDP Mainboard
70
Memory Map of the Local Peripherals
71
Table 32 Peripheral Memory Map
71
Programmer's Reference
72
Supported Tools and Operating Systems
72
Boot Modes
72
Common Boot Modes
72
ARC HS36 Booting from ICCM0
73
Pre-Boot
74
Pre-Boot Overview
74
Default Settings of the DIP Switches on the ARC SDP Mainboard
75
Pre-Boot Mechanism
76
Table 33 Meaning of the Left Character of the Seven-Segment Display
76
Drivers
77
Drivers for Bare-Metal Applications
77
Table 34 Meaning of the Right Character of the Seven-Segment Display
77
Drivers for MQX
78
Bare-Metal Package
78
Overview
78
Table 35 Baremetal Folder Contents
78
Building Bare-Metal Applications Using the Metaware IDE
79
Metaware IDE - Select Workspace Directory
80
Metaware IDE - Importing Existing Projects
80
Metaware IDE - Set Active Build Configurations
81
Table 36 Build Options
81
Metaware IDE - Build Results in Console Window
82
Building Bare-Metal Applications Using Gmake
83
Build Script Options
83
Table 37 Command Line Options for Build.bat
83
Hardware Setup for Debugging
85
Settings of the DIP Switches on the ARC SDP Mainboard for Using the Debugger
85
Location of the Debug Interfaces and the Corresponding Jumpers
86
Location of the ARC SDP Mainboard's Power Supply and Power Switch
86
Running a Bare-Metal Application in the Metaware IDE Debugger
87
Location of the CPU Start Buttons on the ARC SDP Mainboard
87
Table 38 CPU Start Buttons and Display Values for Running Applications in the Debugger
87
Running a Bare-Metal Application in the Metaware Debugger
90
Creating a New Process
90
Debugger Options - Command-Line Options
91
Table 39 Property Arguments for Selecting the CPU Core in the Debugger
91
Debugger Options - Target Selection
92
Specifying a Path to the .Elf File
92
Debugger Status
93
Storing an Image in the SPI Flash and Running the Application
94
Hyperterminal Output
94
MQX Package
96
Overview
96
DIP Switch Settings for Autonomous Code Execution on the ARC Core
96
Building MQX Applications Using Gmake
97
Table 40 MQX Folder Contents
97
Hardware Setup for Debugging
98
Running MQX Applications in the Metaware Debugger
98
Linux and U-Boot Packages
99
Overview
99
Hardware Setup for Debugging
100
Executing the Linux Image with U-Boot
100
Arcv2 Instruction Set: Usage Limitations
107
Software Interfaces
108
Clock-Generation Registers
108
Tunnel Pll
108
Arc Pll
111
AXI Tunnel Address Decoder Registers
114
TUN_A_SLV0: AXI Tunnel Slave Select Register 0
114
TUN_A_SLV1: AXI Tunnel Slave Select Register 1
114
TUN_A_OFFSET0: AXI Tunnel Address Offset Register 0
115
TUN_A_OFFSET1: AXI Tunnel Address Offset Register 1
116
TUN_A_UPDATE: AXI Tunnel Update Register
116
ARC CPU Address Decoder Registers
117
CPU_A_SLV0: ARC CPU Slave Select Register 0
117
CPU_A_SLV1: ARC CPU Slave Select Register 1
117
CPU_A_OFFSET0: ARC CPU Address Offset Register 0
118
CPU_A_OFFSET1: ARC CPU Address Offset Register 1
119
CPU_A_UPDATE: ARC CPU Update Register
119
ARC RTT Address Decoder Registers
120
RTT_A_SLV0: ARC RTT Slave Select Register 0
120
RTT_A_SLV1: ARC RTT Slave Select Register 1
120
RTT_A_OFFSET0: ARC RTT Address Offset Register 0
121
RTT_A_OFFSET1: ARC RTT Address Offset Register 1
122
RTT_A_UPDATE: ARC RTT Update Register
122
PAE Registers
123
PAE: PAE Register
123
PAE_UPDATE: PAE Update Register
123
CPU Start Registers
124
CPU_START: ARC CPU Start Register
124
CPU_0_ENTRY: ARC CPU-0 Kernel Entry Point Register
125
CPU_1_ENTRY: ARC CPU-1 Kernel Entry Point Register
125
CPU_BOOT: Boot Register
125
AXI Tunnel Registers
126
TUN_CTRL Register
126
TUN_STAT Register
126
GPIO Registers
127
GPIO_SWPORTA_DR: GPIO Port a Output Register
127
Table 41 GPIO Port a Output Register (GPIO_SWPORTA_DR)
127
GPIO_SWPORTB_DR: GPIO Port B Output Register
128
Table 42 GPIO Port B Output Register (GPIO_SWPORTB_DR)
128
GPIO_EXT_PORTA: GPIO Port a Input Register
129
Table 43 GPIO Port a Input Register (GPIO_EXT_PORTA)
129
GPIO_EXT_PORTB: GPIO Port B Input Register
130
Table 44 GPIO Port B Input Register (GPIO_EXT_PORTB)
130
Mounting the AXC003 CPU Card
132
Default Settings of the DIP Switches on the ARC SDP Mainboard
133
Installing and Configuring Putty
134
Identification of COM Port
135
Putty Configuration
136
Detailed Core Configurations
137

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