Setting Up Pcie Root Complex Ip Prototyping Kits - Synopsys DesignWare 826-0 Installation Manual

PCIe IP Prototyping Kit Installation Guide
1.2.2

Setting Up PCIe Root Complex IP Prototyping Kits

This section provides instructions for setting up a PCIe Root Complex IP Prototyping Kit hardware, using
the Xilinx, or a Synopsys PCIe PHY board.
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Note Note Note Note
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1. Connect the HAPS-80 and ARC SDP AXS101. These connections depend on the used PHY.
Figure 1-11 shows the connection for setups that use Xilinx PHY.
a. First HT3 cable to the HAPS-80 board on the HT3 track 6 (Xilinx PHY) or track 23 (C10 or E16)
b. Other end of the first HT3 cable to the ARC SDP HT3 track J3.
c. Second HT3 cable to the HAPS-80 board on the HT3 track 7 (Xilinx PHY) or track 24 (C10 or E16).
d. Other end of the second HT3 to the ARC SDP HT3 track J4.
2. Insert the SD card containing the Linux image in the ARC AXS101 SDP system board. You can find
an uImage file in the <workspace>/software/PCI/Linux/main/images/axs101-rc folder
Figure 1-11 HAPS-80 to ARC SDP HT3 Connection
3. To set up the PCIe Root Complex and Endpoint device, make the next connections:
a. Connect the ATX 4 Pin peripheral power connector to the backplane.
b. Make the Root Complex connection:
5.60a
March 2020
To power the PCIe Backplane you need an ATX power supply.
The PCIe Root Complex IPK with E32 PHY uses an ARC HSDK instead of an ARC SDP.
The connection between HAPS-80 and ARC HSDK is different. For instructions follow
"Using ARC HS Development kit" on page 25
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