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Synopsys TSMC180 Data Book

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DWC ADC 12b5M SAR, TSMC180 IP Databook
DWC ADC 12b5M SAR, TSMC180
Databook
3640tg -12-bit, 5MSPS SAR ADC with differential 19:1 Input Mux
Version 1.9
April 2012
April 2012
Synopsys, Inc.
1-30

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Summary of Contents for Synopsys TSMC180

  • Page 1 DWC ADC 12b5M SAR, TSMC180 IP Databook DWC ADC 12b5M SAR, TSMC180 Databook 3640tg -12-bit, 5MSPS SAR ADC with differential 19:1 Input Mux Version 1.9 April 2012 April 2012 Synopsys, Inc. 1-30...
  • Page 2 Synopsys, Inc., or as expressly provided by the license agreement. Destination Control Statement All technical data contained in this publication i s subject to the export control laws of the United States of America.

  • Page 3: Table Of Contents

    Routing of Analog and Reference Signals ................24 ESD / Latch-Up ........................24 Cell Routing Constrains....................25 Connections to the IO PAD ring ................... 26 PCB Guidelines ......................29 Appendix A – Minimum Sampling Time – (Worst case conditions) ........30 April 2012 Synopsys, Inc. 3-30...

  • Page 4: Features

    DWC ADC 12b5M SAR, TSMC180 IP Databook 1 Features General Description  TSMC 180nm G CMOS technology This macro-cell is a power and area optimized  Selectable 12 bit, down to 6 bit Resolution Successive-Approximation ADC, having resolution selectable between 12, 10, 8 and 6 bit. It ...

  • Page 5: Specifications

    DWC ADC 12b5M SAR, TSMC180 IP Databook 4 Specifications Parameter Conditions Unit Technology No analog options TSMC 180nm G CMOS, w ith 3.3V IO devices Minimum metal stack 5m_3x1n supported Metal stack available in 5m_3x1n , 6m_4x1n DWDL Area 0.25 796 x 314 µm*µm...
  • Page 6 DWC ADC 12b5M SAR, TSMC180 IP Databook Parameter Conditions Unit Tim ing Characteristics (Continued) clk falling edge to sampling delay (tsd) soc setup time before clk rising edge (tsocst) soc hold time after clk rising edge (tsochld) clk rising edge to eoc rising edge delay time...
  • Page 7 DWC ADC 12b5M SAR, TSMC180 IP Databook avdd = 3.3V, dvdd = 1.8V, Tjunction= 50°C, fclk=70MHz, f in=50kHz, selres=11 (12-bit mode), seldiff=L (single-ended mode), vrefp=av dd, agndref=0, enldo =H. Parameter Conditions Unit 1.0 2.0 SINAD dBFS 2 Offset error Calibration enabled Calibration disabled 64...

  • Page 8: Pin Description

    DWC ADC 12b5M SAR, TSMC180 IP Databook 5 Pin Description Pin Name I/O Type Function Analog input signals vinp18 .. 0 In differential input mode (seldiff=H), vinp18...vinp1 are the positive inputs, vinn18...vinn1 are Analog the negative inputs. vinp0 available only for single ended input mode.
  • Page 9 DWC ADC 12b5M SAR, TSMC180 IP Databook Pin Name I/O Type Function Parallel Output Bits. The MSB is b11; the LSB is b0 in 12-bit mode, b2 in 10-bit mode, b4 in 8-bit mode and b6 in 6-bit mode. b11..0...

  • Page 10: Operating Modes

    DWC ADC 12b5M SAR, TSMC180 IP Databook 6 Operating Modes This section describes the power-up sequence and the various operating modes that the DWC ADC 12b5M SAR, TSMC180 Table 2 – SAR ADC operating modes. Mode Configuration Deep Pow er-down...

  • Page 11: Deep Power Down Mode

    DWC ADC 12b5M SAR, TSMC180 IP Databook If the offset is not a critical parameter, there is no need to run the calibration cycle. However, there is the need to start a dummy conversion cycle (by setting soc=H, as described in Section 7), before the ADC is ready to receive analog inputs;...

  • Page 12: Standby Mode

    DWC ADC 12b5M SAR, TSMC180 IP Databook “calibrated” conversion cycle started immediately after the Power Up Time has elapsed, (Power Up time corresponds to one dummy conversion cycle). This mode of operation is useful in cases where the power down and start-up sequence is very quick.

  • Page 13: Internal Voltage Regulator

    DWC ADC 12b5M SAR, TSMC180 IP Databook 1000 1400 14000 ADC clock frequency (kHz) Figure 1 – ADC current consumption (single ended mode). The current consumption presented in the previous figure is for the situation where the ADC is operating in successive conversion mode (soc always set to high, check section 7 for more detail).

  • Page 14: Timing Diagrams

    DWC ADC 12b5M SAR, TSMC180 IP Databook 7 Timing Diagrams The Timing Diagram below represents the synchronization between the signals clk, soc, eoc and the output bits. After a conversion cycle eoc is placed at high. A new conversion only begins when soc at high level is detected.
  • Page 15 DWC ADC 12b5M SAR, TSMC180 IP Databook sel4..0 Select Vin(j) channel Select Vin(j+1) channel selres Select ADC resolution Select ADC resolution seldiff Select ADC input mode Select ADC input mode tclk/2 tsocst tsochld teocr teocf b11... b0 Output Data j...
  • Page 16 DWC ADC 12b5M SAR, TSMC180 IP Databook enldo tup_ldo enadc dislvl tloadcalsetup tloadcalhold loadcal bvosi6..bvosi0 bvos6..bvos0 reset tsocst tsochld teocr teocf b11... b0 Sample Vin( n ) tdata Internal Hold Vin(n) Sample Vin( n +1) Dummy Conversion Cycle Figure 5 - Startup Sequence from deep power down mode.
  • Page 17 DWC ADC 12b5M SAR, TSMC180 IP Databook The Figure 7 shows how the sampling time can be increased, to allow the operation with signal sources having a low driving capability: the soc signal is delayed during the number of clock cycles necessary to guarantee the accurate input signal sampling. During this period the input selection bits (sel4..0) must remain unchanged.
  • Page 18 DWC ADC 12b5M SAR, TSMC180 IP Databook 1000 6bit mode - SLOW input 6bit mode - FAST input 8 bit mode - SLOW input 8bit mode - FAST input 10bit mode - SLOW input 10bit mode - FAST input 12bit mode - SLOW input 12bit mode - FAST input 10.0...

  • Page 19: Digital Offset Calibration

    DWC ADC 12b5M SAR, TSMC180 IP Databook 8 Digital Offset Calibration A digital block aids the measurement and correction the offset voltage of the ADC. The calibration cycle is started as shown in the figure below. First it is necessary to reset the digital calibration block, placing resetcal at high for, at least, one clock cycle (a clock falling edge must occur when this signal is high).
  • Page 20 DWC ADC 12b5M SAR, TSMC180 IP Databook Calibration Cycle offset offset offset measurement cycle measurement cycle measurement cycle 17 18 72 73 80 81 ... . resetcal . . .
  • Page 21 DWC ADC 12b5M SAR, TSMC180 IP Databook 9 Production Test A scan chain was added to the core to enable the user to test the digital calibration block separately if desired. Table 3 – Scan mode pins Name Value during Normal Mode Value during test mode...
  • Page 22 DWC ADC 12b5M SAR, TSMC180 IP Databook tclkscan scanclk thld scanrst scanen scanin trsp scanout Figure 13 - Timing diagram of the scan chain signals The scan chain coverage is 96%. All flip-flops are clocked on the rising edge of the scanclk.

  • Page 23: Application Notes

    DWC ADC 12b5M SAR, TSMC180 IP Databook 10Application Notes Cell Placement In addition to employing all known design techniques that reduce the sensitivity to digital switching noise, the SAR ADC is surrounded by shielding guardrings, connected to the p- substrate and to an N-well.

  • Page 24: System Level Clock Issues

    DWC ADC 12b5M SAR, TSMC180 IP Databook System Level Clock Issues To avoid compromising the SAR ADC performance, one should minimize the digital switching activity near its sampling instant. This is accomplished by: 1. Increasing, as much as possible, the time between the sampling instant and the clock edges where there is activity in the digital core(s).

  • Page 25: Cell Routing Constrains

    DWC ADC 12b5M SAR, TSMC180 IP Databook Cell Routing Constrains The table below presents the signals whose routing must follow constrains. Unless otherwise stated the analog signal shielding is made with each cell‟s agnd (or avdd as 2 option). Table 4 – ADC signals with routing constrains...

  • Page 26: Connections To The Io Pad Ring

    DWC ADC 12b5M SAR, TSMC180 IP Databook 12 Connections to the IO PAD ring The figures below indicate how the connections between the cell and the IO PAD ring should be made. The following notation is used:  PVDD1 is a generic 3.3V Power PAD to bias both the IO ring and the core cell.
  • Page 27 DWC ADC 12b5M SAR, TSMC180 IP Databook The following figure shows the configuration for differential inputs, with the negative reference connected to ground internally in order to save package pins. vrefp is connected to a pad. In the case of single ended inputs, the unused negative input should be connected to agndref.
  • Page 28 DWC ADC 12b5M SAR, TSMC180 IP Databook The following figure shows the configuration for differential inputs, with the negative and positive references connected to ground internally in order to save package pins. In the case of single ended inputs, the unused negative input should be connected to agndref.

  • Page 29: Pcb Guidelines

    DWC ADC 12b5M SAR, TSMC180 IP Databook 13 PCB Guidelines Power supply decoupling should be done according to the figure below. At least the 10nF capacitors should be ceramic (good quality), and must be placed as close as possible to the chip.

  • Page 30: Appendix A - Minimum Sampling Time - (Worst Case Conditions)

    DWC ADC 12b5M SAR, TSMC180 IP Databook Appendix A – Minimum Sampling Time – (Worst case conditions) Min sampling Min sampling Rin(kΩ) Rin(kΩ) Input Resolution Input Resolution time (ns) time (ns) 0.05 0.05 12-bit 12-bit 1690 1690 4190 4200 8350 8350 0.05...

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