Processor Technology CUTS Assembly And Test Instructions page 52

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JUMP
CALL
RETURN
RESTART
ROTATE+
MOVE
(conti
ACCUMULATOR*
CONSTANT
DEFINITION
C3 JMP
CO CALL
C9 RET
C7 RST 0
07
ALC
58
MOV E,B
80
ADD B
A8
XRA B
C2 JNZ
C4 CNZ
CO RNZ
CF RST
1
OF
RAC
59
MOV E,C
81
ADD C
A9
XRA C
OBDHf
CA JZ
CC CZ
C8 RZ
07 RST 2
17
RAL
5A
MOV E,O
82
ADD 0
AA
XRA 0
lAH Hex
02 .JNC
04 CNC
DO RNC
OF RST 3
IF
RAR
5B
MOV E,E
83
ADD E
AB XRA E
DA JC
Adr
DC CC
Adr
08 RC
E7
RST 4
5C MOV E,H
84
ADD H
AC XRA H
1050 f
.
E2
JPO
E4
CPO
EO
RPO
EF RST 5
50 MOV E,L
85
ADD L
AD XRA L
105 Decimal
EA JPE
EC CPE
E8
RPE
F7
RST 6
5E
MOV E.M
86
ADD M
AE XRA M
F2
JP
F4
CP
FO
RP
FF
AST 7
CONTROL
5F
MOV E,A
87
ADD A
AF XRA A
720f
FA JM
FC CM
F8
RM
720
Octal
E9
PCHL
00
NOP
60
MOV H,B
88
AOC B
BO
ORA B
76
HLT
61
MOV H,C
89
AOC C
Bl
ORA C
11011B} .
F3
01
62
MOV H,O
8A AOC 0
B2 ORA 0
00110B Binary
FB
EI
63
MOV H,E
8B AOC E
B3
ORA E
MOVE
Ace
LOAD
64
MOV H,H
8C AOC H
B4 ORA H
'TEST' }
IMMEDIATE
IMMEDIATE*
IMMEDIATE
STACK OPS
65
MOV H,L
80 AOC L
B5
ORA L
'A' 'B' ASCII
66
MOV H.M
8E
AOC M
B6
ORA M
06
MVI
S.
C6 AOI
01
LXI
B
I
C5
PUSH B
MOVE
67
MOV H.A
8F
AOC A
B7
ORA A
OE
MVI
C.
CE ACI
11
LXI
~:
016
05
PUSH 0
MOV
SUB
CMP
OPERATORS
16
MVI
O.
06
SUI
21
LXI
E5
PUSH H
40
MOV B,B
68
L,B
90
B
B8
B
1E
MVI
E.
DE SBI
31
LXI
SP.
F5
PUSH PSW
41
MOV B,C
69
MOV L.C
91
SUB C
B9
CMP C
26
MVI
H
08
E6
ANI
08
42
MOV B,O
6A
MOV L.D
92
SUB 0
BA CMP 0
2E
MVI
L.
EE
XAI
Cl
POP B
43
MOV B,E
6B
MOV L.E
93
SUB E
BB CMP E
MOV B.H
6C MOV L,H
94
SUB H
BC CMP H
+ -
36
MVI
M.
F6
ORI
01
POP 0
44
3E
MVI
A.
FE
CPI
E1
POP H
45
MOV B.L
60 MOV L,L
95
SUB L
BO CMP L
DOUBLE ADD+
Fl
POP PSW·
46
MOV B.M
6E
MOV L.M
96
SUB M
BE CMP M
09
DAD B
47
MOV B,A
6F
MOV L,A
97
SUB A
BF CMP A
19
DAD 0
E3
XTHL
48
MOV C.B
70
MOV M,B
98
SBB
B
29
DAD H
F9
SPHL
49
MOV C,C
71
MOV M,C
99
SBB C
PSEUDO
STANDARD
INCREMENT**
DECREMENT"''''
39
DAD SP
4A
MOV C.O
72
MOV M,O
9A
SBB
0
INSTRUCTION
SETS
4B
MOV C,E
73
MOV M.E
9B
SBB
E
04
INR
S
05
OCR B
SPECIALS
4C
MOV C,H
74
MOV M,H
9C SBB
H
ORG Adr
A
SET
7
OC
INR
C
00
OCR
C
40
MOV C,L
75
MOV M.L
90 SSB
L
END
B
SET
0
14
INR
0
15
OCR 0
LOAD/STORE
EB XCHG
4E
MOV C,M
._------------
9E
SBB
M
EOU 016
C
SET
1
1C INR
E
10
OCR E
27
DAA'
4F
MOV C.A
77
MOV M,A
9F
SSB A
0
SET
2
?4
INR
H
25
OCR H
OA
LDAX B
2F
CMA
OS
016
E
SET
3
2C
INR
L
20
OCR L
1A
LDAX 0
37
STCt
50
MOV D.B
78
MOV A.B
AO
ANA B
DB
08
( I
H
SET
4
34
INR
M
35
OCR M
2A
LHLD Adr
3F
CMC+
51
MOV D,C
79
MOV A,C
Al
ANA C
OW
016
"
L
SET
5
3C
iNR
A
3D
OCR A
3A
LOA
Adr
52
MOV 0,0
7A
MOV A,O
A2
ANA 0
M
SET
6
53
MOV D,E
7B
MOV A,E
A3
ANA E
SP SET
6
03
INX
B
DB
OCX B
02
STAX B
INPUT/OUTPUT
54
MOV O.H
7C MOV A,H
A4
ANA H
PSWSET 6
13
INX
0
1B OCX 0
12
STAX 0
55
MOV O,L
70 MOV A,L
A5
ANA L
23
INX
H
2B
DCX H
22
SHLD Adr
03 OUT 08
56
MOV D,M
7E
MOV A,M
A6
ANA M
33
INX
SP
3B
DCX SP
32
STA
Adr
DB IN
08
57
MOV D,A
7F
MOV A,A
A7
ANA A
08
constant, or logicaL-arithmetic expression that evaluates
016 - constant, or 10gicaVarithmetic expression that evaluates
Adr
~
16 bit address
to an 8 bit data quantity.
to a 16 bit data quantity.
••
~
all Flags except CARRY affected;
»
"0
all Flags (C.Z.S.P) affected
t
=
only CARRY affected
(exception: INX
&
DCX affect no Flags)
"0
m
:2
~
0
H
X
H
I
© Processor Technology Corp.
I\)

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