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PROCESSOR TECHNOLOGY CORPORATION
CUTS, COMPUTER USERS TAPE SYSTEM
SECTION V
The clock for U2 is 2400 Hz in the high speed mode or 4800
Hz in the low speed mode.
This clock is derived from the 2400 Hz
output of UIO in conjunction with the low speed select signal NAND
gate Ul and exclusive-OR gate U19.
In the high speed mode, pins 4 and 5 of Ul are held low,
thus holding pin 6 of Ul high.
As a result the 2400 Hz signal is
inverted in Ul19 to become the clock for U2.
Pins 4 and 5 of Ul are held high, however, in the low speed
mode to enable Ul.
In this case R19 and C20 provide a delay in the
Ul gate.
When the 2400 Hz signal on pin 9 of U19 changes state; so
does pin 10 of U19.
Also, C20 charges through R19 for several hun-
dred nanoseconds, at which point pin 6 of Ul is brought to the op-
posite polarity.
The output from U19 then goes high.
A series of
positive pulses, with a pulse width approximately equal to the R19,
C20 time constant and occuring at every transition of the 2400 Hz
signal, appears on pin 10 of U19.
This circuit thus operates as a
frequency doubler in the low speed mode to provide a 4800 Hz clock
for U2.
The 2400 Hz signal from which the U2 clocks are derived al-
so produces the 1200 Hz clock signal for U3 by toggling the flip-
flop in UIO.
As a result the 1200 Hz signal changes state follow-
ing a propagation delay after the 2400 Hz signal falls.
As previously stated, the second stage of U2 is allowed to
change state on the positive going transitions of the U2 clock as
long as the data out of the synchronizer is a 11111.
The end result
is an output on pin 2 of U2 that is one-half the clock frequency
(1200 Hz and 2400 Hz in the high and low speed modes respectively).
Assume the data stream out of the UART goes low (110 11 ).
On
the next rising edge of the 1200 Hz signal, U3 will reset with Q
low and
Q
high.
A low reset on pin 12 of U2 enables the first U2
stage to toggle on the next rising edge of the U2 clock which occurs
1/2400 second after the synchronizer output falls.
Remember that
the U2 clock moves from a lqw to a high shortly before the 1200 Hz
signal did.
The reset on pin 12 of U2 is thus removed slightly
after the U2 clock occurred.
with the
J
and K inputs to the first
U2 stage high, its output will change state on each succeeding low
to high transition of U2 clock.
The second U2 stage in turn can
only toggle on the positive going transition of U2 clock when its
J
and K inputs are high.
Since the inputs are high at one-half the
clock rate, by virtue of the first U2 stage, the second U2 stage
toggles at one-fourth the clock rate.
The two sections of U2, therefore, operate as a frequency
divider, dividing the clock by two when the write data is a 11111
and by four when the data is a 110 11 •
Thus, in the low speed mode,
four cycles of the 1200 Hz represent a 110 11 and eight cycles of
2400 Hz represent a 11111.
In the high speed mode, one cycle of
V-7
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