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PROCESSOR TECHNOLOGY CORPORATION
CUTS, COMPUTER USERS TAPE SYSTEM
SECTION V
Table 5-1.,
Strobe Decoder (U23) Truth Table.
INPUTS
ACTIVE
CARD
OUTPUT
- -
A¢*
SELECT
PDBIN*
SINP*
PWR*
SOUT*
(Low)
L
H
H
H
-
-
READ STATUS
H
H
H
H
-
-
DATA READ STROBE
L
H
-
-
L
H
STATUS WRITE STROBE
H
H
-
-
L
H
DATA WRITE STROBE
*Inputs to CUTS module.
The remaining control circuit, POC (power on clear), ini-
tializes the CUTS whenever power is applied.
When power is applied,
POC on S-IOO bus pin 99 goes low.
POC is inverted in one section of
U21 to clear the logic in the UART (UlS).
In addition, the inverted
POC is again inverted in one section of U24 to clear the status re-
gister, U13.
This clear sets both motor control outputs as well as
the high
speed select bit high.
5.3.3
write Mode
When the CUTS is in the write mode, data is input to the
UART (UlS) under control of the DATA WRITE STROBE signal from U23.
Upon completion of this strobe, the transmit sequence is initiated
within the UART, with the transmission rate being governed by WRITE
CLOCK.
The transmission sequence begins with a start bit, a low
(data zero) on the UART's TO output.
It is followed by eight data
bits and two stop bits, with the number of bits being fixed by the
connections to pins 34 through 39 of UIS.
This data stream is
called NRZ data (non-return to zero) because the data never returns
to zero until the next bit cell.
NRZ data from UIS is applied to the D input of U3, aD-type
flip-flop which is clocked at 1200 Hz.
Consequently, the output on
pin 13 of U3 follows the input data on pin 9 after the rising edge
of the 1200 Hz clock.
This output is connected to the reset (pin 12)
of U2, so when the data out of the UART is high, the first section
in U2 is forced to a reset condition.
In this condition the
J
and K
inputs to the second stage of U2 are held high which allows the flip-
flop to change state on the rising edge of the clock.
V-6
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