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PROCESSOR TECHNOLOGY CORPORATION
CUTS, COMPUTER USERS TAPE SYSTEM
SECTION V
been accepted.
It also resets the driver enable generator to imme-
diately enable the DI bus drivers.
If the cycle is an output cycle and A¢ is high, the strobe
decoder outputs a DATA WRITE which transfers DO bus data into the
UART and initiates serial transmission by the UART.
Should A¢ be
low, the strobe decoder outputs a STATUS WRITE.
STATUS WRITE
strobes the data on D04-7 into the status latch.
The four status bits in this latch are concerned with record-
er motor control and data rate.
One output turns one recorder motor
on and off, another turns a second recorder motor on and off, a
third selects a low data rate, and the fourth selects a high data
rate.
Timing for the CUTS module is supplied by the clock circuits
and read clock.
Clock circuitry manipulates ¢2 to supply WRITE
CLOCK as well as various other timing signals required to obtain two
data rates.
Read clock uses NRZ data transitions and one of two
clock signals to generate READ CLOCK for use in the read mode.
When CUTS is in the write mode, parallel data on DO¢-7 is
serialized in the UART and applied to a synchronizer in the NRZ for-
mat.
The synchronizer in turn establishes the time at which the bit
cell from the UART starts.
The digital-to-audio converter converts
the data bit levels into corresponding audio signals.
These signals
are then fed through a driver to the audio output jacks.
In the read mode, inputs from the recorders are mixed and
amplified, with an AGC circuit operating on the second stage.
Fol-
lowing amplification the audio signals are converted into digital
signals, the transitions of which are detected and converted into
the NRZ format.
NRZ data is applied to the UART which performs the
required serial-to-parallel conversion and supplies the parallel
data to the DI bus drivers.
5.3
THEORY OF OPERATION
Refer to CUTS schematic in section VI.
5.3.1
Timing
All timing for the CUTS module is derived from, or related
to, the 2 MHz ¢2 clock from the computer.
As can be seen on the
schematic, ¢2 is received on pin 24 of the S-IOO bus by a hysteresis
receiver, U21.
The inverted ¢2 directly clocks both sections of U20
as well as U12.
One half of U20 (clock pin 12) serves as the wait
state
generator~
the other half generates the DRIVER ENABLE signal.
U12, preset to count 3, divides ¢2 by 13 to produce a 153.85
KHz signal on pin 11.
The output of U12 is in turn counted down in
V-2
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