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PROCESSOR TECHNOLOGY CORPORATION
CUTS, COMPUTER USERS TAPE SYSTEM
SECTION V
output on pin 3 of u19 is also low and the output on pin 11 of u19
is high.
The voltage across C22 under this condition is minimal.
When the output of U22 goes high, C22 starts to charge through R20
until pin 2 of U19 crosses the threshold of that gate.
At this
point pin 3 of U19 goes high, and since the two inputs to the se-
cond exclusive-OR gate are both high, pin 11 of U19 goes low.
C22
now discharges because pins 2 and 3 of U19 are at the same level
so that the circuit can repeat the operation on the next high to
low transition at pin 4 of U22.
R20, C22 and U19 consequently
serve as a transition detector that produces a pulse less than one
microsecond long for each transition of the output on pin 4 of U22,
regardless of the polarity of the transition.
Transition pulses from U19 clock
~
of U3 and
~
of U4, both
of which are D-type flip-flops.
A transition pulse clocks U3 to set
Q
high and Q low to enable a binary counter, US.
The
Q
output of U3
is applied to pin 5 of U4 and the circuit remains in this state
until one of two things occurs:
1) a second transition pulse ar-
rives before US reaches count 12 or 2) uS reaches count 12.
If a second transition pulse arrives before count 12, the
first U4 stage is set and presents a 11111 to pin 9 of U4. - This is
clocked by the -reset of U3 as a low to pin 12 of U4.
If a transition pulse does not arrive before count 12, the
first U4 stage presents a 110" to pin 9 of U4.
On count 12, the C
and D outputs of US go high to reset U3 through Ul.
As a result
the U4 second stage clock goes high, as does pin 12 of U4.
The
output on pin 12 of U4, in the NRZ format, is inverted by U22 and
applied to the receive input of the UART.
The Q output of U3, which occurs at the actual bit rate of
the incoming data, is also used by the receive clock circuitry to
reconstruct the receive clock from the data signal.
Received data undergoes serial-to-parallel conversion in the
UART and placed on the ROl-S data outputs of the UART WHEN ROD
(pin 4 of the UART) is low.
The received data is then gated through
u16 and 17 to the DI bus.
Four status outputs from the UART can also be enabled when
SFD (pin 16) is low.
These four bits are FE (framing error), OE
(overrun error), DR (data ready) and TBRE (transmitter buffer re-
gister empty).
They are also gated through U16 and 17 to DI3,4,6
and 7 respectively by a delayed READ STATUS signal.
V-9
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