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PROCESSOR TECHNOLOGY CORPORATION
CUTS, COMPUTER USERS TAPE SYSTEM
SECTION V
UlO, a seven-stage binary counter, to provide 38.4 KHz on Q2, 19.2
KHz on Q3, 4800 Hz on Q5, 2400 Hz on Q6 and 1200 Hz on Q7.
The
clocks on Q6 and Q7 are used in the write data synchronizer (U3) and
and the digital-to-audio converter (U2).
The remaining outputs from UIO are fed to two sections of U9,
a quad multiplexer or select gate.
All four sections of U9 are used
to select clocks for low speed or high speed operation according to
the select inputs, pins 9 (a) and 14 (B).
The states of these two
select inputs must be complementary to each other in order to select
the high or low speed clocks.
Specifically, A must be high and B
low to select high speed clocks: the converse condition selects low
speed clocks.
The select inputs are supplied by the complementary
outputs of one section in U13, the status latch.
The output of the second section of U9 is WRITE CLOCK, 4800
Hz on low speed and 19.2 KHz on high speed.
The third section out-
puts a 19.2 KHz (high speed) or 38.4 KHz (low speed) timing signal
to U8 in the NRZ data conversion circuit.
READ CLOCK is produced by ull (a phase locked loop), U8 (a
binary counter) and the remaining two sections in U9.
The signal
input (pin 14) to ull is supplied from pin 1 of U3 in the NRZ data
conversion circuit.
It is a constant frequency, regardless of whe-
ther one or two transitions are detected in the read data during the
count out time (12 counts) of the counter (U8) in the NRZ conversion
circuit.
A phase comparator in Ull compares the signal input to the
output of a voltage controlled oscillator (VCO) in Ull (pin 4).
By
feeding the VCO output through a counter (the other half of U8) be-
fore feeding the counter output back to the compare input (pin 3)
of Ull, the circuit acts as a frequency multiplier.
The output of
this circuit remains locked, therefore, to a multiple of the signal
input on pin 14 of Ull.
The output of ull is nominally 19.2 KHz.
Remember that the
actual output is determined by the signal input which in turn is a
function of tape speed.
In other words, the phase lock loop circuit
tracks input frequency variations.
And it will track such varia-
tions within its locking range which is determined by the setting of
VRI (connected to pin 12 of Ull).
On high speed, the divide by four output of U8 (pin 12) is
selected as RECEIVE CLOCK.
The VCO output of Ull is selected for
the low speed RECEIVE CLOCK.
5.3.2
Control
Basically the wait state generator
(~
of U20), address se-
lector and decoder (Sl, u14 and U15), strobe decoder (U23), driver
enable generator
(~
of U20), the status latch (U13), the status in/
out decoder (U14 and 24), motor control (Kl and 2), and power on
clear (U21) comprise the CUTS control circuitry.
V-4
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