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PROCESSOR TECHNOLOGY CORPORATION
CUTS, COMPUTER USERS TAPE SYSTEM
SECTION V
The address selector and decoder consists of seven open col-
lector exclusive-OR gates, the inputs of which are connected to
Al-~
RXI and Sl.
RXI and Sl function as the selector which is configured
to reflect the complement of the module address.
That is, a response
to a high on an address line is generated by the applicable gate by
grounding the other input by closing the appropriate DIP switch
position.
When the decoder senses an address match, all the gates
respond true and RX2-4 pulls the outputs up to a high level CARD
SELECT signal.
CARD SELECT enables the output gate (U2l) in the status in/
out decoder.
This gate is satisfied if, and only if, SOUT or SINP
is active to indicate either an input or output operation is under
way.
The output (pin 6) of U2l enables the PRDY line driver.
The input to this driver is provided on pin 10 of U20, the
wait state generator which is clocked by ¢2 and reset by PSYNC.
Thus, pin 10 of U20 goes high on the falling edge of ¢2 after PSYNC.
This is the time during which the processor tests for wait requests.
The purpose of this half of U20, therefore, is to insert one wait
state into every input or output request by the processor.
This is
required to lengthen the data strobes to durations required by the
UART.
U23, the strobe decoder, decodes SINP, PDBIN, SOUT, PWR
and A¢ to produce STATUS WRITE, READ STATUS, DATA READ STROBE, and
DATA WRITE STROBE.
The truth table for U23 is provided in Table
S-l on Page V-6.
All outputs from U23 are low active.
READ STATUS is applied to the
J
and K inputs to the other
half of U20 which is clocked by ¢2.
Thus, an active READ STATUS
signal produces a DRIVER ENABLE which is delayed from the strobe by
one-half a ¢2 cycle.
This signal enables the tri-state buffers
(U16 and 17) to place data on the DI bus.
Note that a DATA READ
STROBE resets U20 to immediately enable the DI bus buffers.
The status latch, U13, latches data present on D04-7.
(Note
that the data on D04 is not used.)
Data is loaded into U13 when the
strobe decoder outputs a STATUS WRITE STROBE.
Four output bits from
this latch select data rate and control the tape recorders.
A low
on pin 14 energizes K2 to turn recorder #1
on~
a high on this pin
de-energizes K2 to turn recorder #1 off.
The output on pin 11 of
U13 does the same thing for Kl which controls "recorder #2.
(Dl and
D2, which shunt K2 and Kl respectively, prevent damage to the logic
circuitry due to inductive kickback.)
The remaining two outputs
from U13, the complementary outputs associated with DOS, select
either low or high speed operation by selecting the appropriate
clocks out of U9.
Low speed is selected when pins 3 and 2 of U13
are high and low respectively.
When the converse relationship
exists, high speed is selected.
V-S
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