MOGlabs ARF021 Manual page 118

108
Note: The external reference clock must have power between -10dBm and +10dBm.
The output of the
to ensure that synchronisation was successful. Never operate the
nal clock mode without providing a valid reference clock, as undefined behaviour
can result.
CLOCK
CLKDIAG
If the clock source is 1 GHz, then
disables the PLL
Except for this special case, valid ranges for
means the reference must be the range 7.87 MHz to 83.3 MHz.
CLOCK
command should be checked after using the
CLOCK,ch
Measures the current
channel, as measured by the
should return 1000 MHz, indicating that the system is correctly syn-
chronised to the clock source. If it does not, use
whether the PLL has achieved a lock to the reference.
Drift between the internal and external clocks can result in small
shifts in this measurement.
CLKDIAG
Reports diagnostic information about the status of the internal clocks.
In regular operation, the Reference, System and DDS clocks should
always report "OK LOCKED".
SYNC
If the feature is used then the Sync clock should also be report
locked status.
Failure of any of the
and is typically a result of the reference clock having incorrect am-
plitude or excessive phase noise.
Appendix C. Command language
ppln
and improves the phase-noise of the
DDS system clock frequency for the specified
FPGA over a one second window. This
PLLs to lock can result in undefined behaviour,
must be set to zero. This
RF
ppln
are [12,127], which
CLKSRC
command
in exter-
ARF/XRF
CLKDIAG
to determine
output.