Page 1 Agile RF Synthesizer & AOM driver ARF021/ARF421, XRF021/XRF421 Version 1.7.4, Rev 8 hardware...
Page 2 MOGL abs. Contact For further information, please contact: MOG Laboratories P/L MOGLabs USA LLC 49 University St 419 14th St Carlton VIC 3053 Huntingdon PA 16652 AUSTRALIA +61 3 9939 0677 +1 814 251 4363 info@moglabs.com...
Page 3 We hope that you enjoy using the ARF/XRF , and please let us know if you have any suggestions for improvement in the ARF/XRF or in this document, so that we can make life in the lab better for all. MOGL abs, Melbourne, Australia www.moglabs.com...
Page 5: Safety Precautions
Safety Precautions Safe and eﬀective use of this product is very important. Please read the following safety information before attempting to operate. Also please note several speciﬁc and unusual cautionary notes before using the MOGL ARF/XRF , in addition to the safety precautions that are standard for any electronic equipment.
Page 6: Protection Features
Protection Features MOGL ARF/XRF includes a number of features to protect you and your device. Open/short circuit Each output should be connected to a 50 Ω load. The F/XRF will disable each high-power output if not connected or if a short-circuit is detected. Reﬂected power The reﬂected power and VSWR (voltage standing wave ratio) are monitored and...
Page 7: Table Of Contents
Contents Preface Safety Precautions Protection Features 1 Introduction 1.1 Operating modes ..... 1.2 Feature compatibility ....on/oﬀ...
Page 8 Contents 5.3 Dual modulation: fast and slow modes ..5.4 Examples ......6 PID stabilisation 6.1 Signal conditioning .
Page 9 Contents 9.8 Other instruction parameters ....9.9 Additional examples ....A Speciﬁcations B Firmware upgrades B.1 Firmware components .
Page 10 Contents viii...
Page 11: Introduction
1. Introduction MOGL ARF/XRF consists of two independent AD9910 direct digital synthesizer (DDS) sources, each with 4 W ampliﬁer. The frequency, amplitude and phase of each output is software-controlled via a microcontroller and (ﬁeld programmable gate array). This FPGA enables direct control of the frequency, amplitude and phase of the signals, which can be adjusted in real-time using the front-panel control knobs, or via a scripting language over ethernet or .
Page 12: Operating Modes
Chapter 1. Introduction then further ampliﬁed with a GaN hybrid high-power output stage ARF421/XRF421 only). The signals are monitored to check output power and to measure the reﬂection ( VSWR chips are controlled by the FPGA . A microcontroller provides external interface with TCPIP communications, and controls...
Page 13: Advanced Mode
1.1 Operating modes : Basic mode Default state on power-up. In this mode, each channel acts as a simple single-frequency source, with the chips controlled directly by the FPGA . The frequency and power of the signal can be controlled via the front panel, using simple instructions over the FREQ computer interface (e.g.
Page 14: Feature Compatibility
Chapter 1. Introduction 1.2 Feature compatibility ARF/XRF provides a wide range of functionality, but not all fea- tures are compatible with each other. The following table sum- marises which features can be used in which modes. Front-panel controls External modulation ( AM/FM/PM control Direct...
Page 15: Connections And Controls
2. Connections and controls 2.1 Front panel controls ADJUST Agile RF Synthesizer ON/OFF CHANNEL 1 CHANNEL 2 Figure 2.1: Front-panel layout of R 8 ARF/XRF devices. Other revisions may have a diﬀerent appearance. Starting with devices, the front-panel includes an interactive menu system for controlling the device.
Page 16 Chapter 2. Connections and controls Figure 2.2: The main menu shows the current state of each channel. Left: both channels are in basic mode, with enabled on , and enabled on . Right: is in basic table mode, with the number of entries in the table shown.
Page 17 2.1 Front panel controls When an editable (yellow) value is selected, turning the encoder wheel changes the value of the selected digit as identiﬁed by the arrow and red text. To change the digit of interest, either use the < or >...
Page 18: Rear Panel Controls And Connections
Chapter 2. Connections and controls 2.2 Rear panel controls and connections RF OUT 1 FM/PM 1 FM/PM 2 CLK IN RF OUT 2 MON 1 AM 1 AM 2 MON 2 Model: 90-264 Vac Serial No: 47-63 Hz IEC power in is compatible with all standard power systems, from 90 to 264 V and 47 to 63 Hz.
Page 19: Internal Dip Switches
2.3 Internal DIP switches XSMA breakout board is available to provide convenient connectors for each I/O channel (§7.3). RJ45/USB-A Ethernet (TCP/IP 10/100 Mb/s) and communications jacks. 2.3 Internal DIP switches Four switches are provided to assist in diagnosis and recovery of the ARF/XRF units.
Page 20 Chapter 2. Connections and controls...
Page 21: Communications
3. Communications can be connected to a computer by or ethernet ( TCPIP The software package mogrf (chapter 4) provides interactive func- tionality, or communications can be integrated into existing control software. Examples of controlling the in several languages ARF/XRF are provided in Appendix D.
Page 22 Chapter 3. Communications > FREQ,1 < 80.00000009 MHz (0x147AE148) > FREQ,3 < ERR: Invalid channel, 3 In the above example, the frequency query provides a value ﬁrst in MHz as well as the internal setting (called the “frequency tuning word”) as hexadecimal in brackets. It is strongly recommended that all software should wait for this response and check whether it indicates an error before continuing.
Page 23: Tcp/Ip
3.2 TCP/IP 3.2 TCP/IP ARF/XRF can be accessed over ethernet via the IPv4 protocol. When ethernet is connected, the will attempt to obtain an address by DHCP . If DHCP fails, an internally deﬁned address will be used. In both cases, the address will be shown on the device display (for example, 10.1.1.190:7802), showing the address and port number for communicating with the device.
Page 24: Usb
Chapter 3. Communications 3.3 USB ARF/XRF can be directly connected to a host computer using a USB cable (type A-male). The device will appear as a Virtual port - a fast serial port that behaves like an RS232 connection. The required STM32 Virtual COM Port Driver ) device driver is available from the...
Page 25 3.3 USB Note that if the port appears in Device Manager with a diﬀerent name, then the driver was not successfully installed. If this occurs, disconnect the device from the host computer, reinstall the VCP driver, then reconnect the USB cable. The mogrf host software (§4) automatically enumerates the avail- able ports when started, making device identiﬁcation simpler.
Page 26 Chapter 3. Communications...
Page 27: Mogrf Host Software
4. MOGRF host software The mogrf software package provides a simple user interface to the basic behaviour of ARF/XRF devices, with the ability to issue commands, run scripts, control tables, and apply ﬁrmware updates. Please note: It may be necessary to install a ﬁrmware update (see Appendix B) to use the software described in this section.
Page 28: Device Commander
Chapter 4. MOGRF host software 4.2 Device commander The Device commander is an interactive terminal for issuing com- mands and queries to your device and displaying the result ARF/XRF (Figure 4.2). The accepted commands and their functions are listed in Appendix C. Type statements into the Command box and exe- cute them by pressing the key or clicking .
Page 29: Mogrf Main Window
4.3 MOGRF main window 4.3 MOGRF main window The main window of mogrf is shown below. The two channels are displayed side-by-side, with information and controls that depend on the current operational mode of each channel. Figure 4.3: The main window of mogrf, showing Channel 1 in normal (NSB) mode and Channel 2 in simple table (TSB) mode.
Page 30: File Menu
Chapter 4. MOGRF host software 4. Channel output can be controlled by enabling only the switch (signal), ampliﬁers (power) or both (421-series only). 5. Options to enable external control of the channel output connector (see §7.6). using the input on the DE15 6.
Page 31 4.3 MOGRF main window 4.3.2 Settings menu Ethernet Allows conﬁguration of network connection settings ( address, mask, gateway and port). Particularly useful for conﬁguring the network . Note that changing the Static IP only has an settings over eﬀect if DHCP is disabled, or if DHCP...
Page 32 Chapter 4. MOGRF host software Figure 4.5: Modulation settings interface, showing that simultaneous FM and AM is enabled on Channel 1, with high bandwidth on AM. PID is disabled but constants have been set. Download settings Downloads conﬁguration and calibration data from the device and stores it in a ﬁle for backup purposes.
Page 33 MOGL abs for analysis. Figure 4.6: Diagnostic information about the connected unit, which should be sent to MOGLabs for analysis if there is a problem with the device. About Displays version information about the mogrf toolkit and connected ARF/XRF...
Page 34: Table Viewer
Chapter 4. MOGRF host software 4.4 Table viewer mode), mogrf provides a viewer for in- In simple table mode ( specting both the table instructions currently loaded into each chan- nel, as well as the instructions stored in FLASH memory (Figure 4.7). This is beneﬁcial for cataloguing the sequences in memory, as well as for debugging sequences which have been generated by scripts and uploaded to the device.
Page 35: External I/O Settings
4.5 External I/O settings 4.5 External I/O settings ARF/XRF provides extensive digital I/O capability through the EXTIO command and conﬁguration window (Figure 4.8). It displays the current input and output state of the I/O pins on both the DE15 connector (§7.1) and the high-speed banks (§7.2). This is to diag- nose the I/O state, and that any settings are correct for the desired application.
Page 36 Chapter 4. MOGRF host software 4. Analog monitoring signal currently output on the analog out- put pin of the DE15 connector. 5. Current state of the two high-speed banks. The banks are dis- abled (black) on boot, and must be set to either read (yellow) or write (green) mode on a per-bank level.
Page 37: External Modulation
5. External modulation ARF/XRF supports external modulation of the mode through the modulation input connectors on the back-panel. Frequency, amplitude and phase modulation of the are supported, and dual-modulation is possible for simultaneous FM/AM FM/PM WARNING: The modulation inputs are nominally ±1V, and can be permanently damaged by applying higher voltages.
Page 38: Modulation Gain
Chapter 5. External modulation 5.2 Modulation gain The modulation depth is controlled by the “gain” and is set using GAIN command. Each modulation mode (amplitude, frequency or phase) has a separate modulation gain for individual control, and can be negative to indicate that the modulation action is inverted. The gain can be speciﬁed either with physical units, or using an integer representation.
Page 39 5.2 Modulation gain Max gain (hex) 0x3FFF8000 0x3FFF 0xFFFF Max gain (dec) 1,073,709,056 16,383 65,535 ◦ Step size 0.23 Hz 0.006% Max 0 0055 ◦ Max modulation 250 MHz 100% Max Table 5.1: Gain ranges for diﬀerent modulation modes. Based on these values and ignoring discretisation and saturation, an applied voltage will have the following eﬀective modulation: = (0 23 Hz/V)G V Frequency:...
Page 40: Dual Modulation: Fast And Slow Modes
Chapter 5. External modulation • To amplitude modulate by ±50% in an ARF421 at an average power of +30 dBm, use the command to determine that the amplitude is 0x2000 = 8192, and set the gain to 8192 × 0 5 = 4096. 5.3 Dual modulation: fast and slow modes ARF/XRF is capable of dual modulation, where the...
Page 41: Examples
5.4 Examples 5.4 Examples 5.4.1 Simple linear ramps Listing 5.1 shows simultaneous linear ramping of amplitude and fre- quency (Figure 5.1). A linear ramp is connected to both the FREQ1 AMPL1 modulation inputs in parallel. Subsequently increasing gain results in clamping the amplitude to respect the limit LIMIT set by the command (Figure 5.2).
Page 42 Chapter 5. External modulation Figure 5.2: Demonstration of high gain amplitude modulation showing LIMIT clipping at zero and the power limit set by the command. 5.4.2 Comparison of fast and slow modulation FMSPEED Figure 5.3 compares the result of diﬀerent settings when applying a 1 V sine wave at 100 kHz to the...
Page 43 5.4 Examples Figure 5.3: Comparison of the output waveform (blue) with FMSPEED,FAST FMSPEED,SLOW (top) and (bottom) when performing amplitude modulation with a 100 kHz sine-wave input (green).
Page 44: Phase Modulation
Chapter 5. External modulation 5.4.3 Phase modulation The two channels of the ARF/XRF can be used to perform phase modulation experiments whereby is used to demodulate Using phase modulation mode with a 1 Vpp modulation input with gain 0x7fff gives ±π phase modulation (Figure 5.4). Figure 5.4: A 1 Vpp, 10 kHz triangle wave (blue) is used for phase mod- ulation of and demodulated with an unmodulated...
Page 45: Pid Stabilisation
6. PID stabilisation In addition to external modulation, the ARF/XRF mode also implements control loops which can be used in conjunction with to perform intensity or frequency stabilisation of a laser. Each channel has an independent controller, which acts to drive an “error signal”...
Page 46: Pid Control Loop
Chapter 6. PID stabilisation ing circuit should be used to ensure that the signal fed into the does not exceed the ±1 V modulation input tolerance, as ARF/XRF this can damage the input ADCs For convenience, MOGL abs produces a signal-conditioning board B3120 ) available as an optional extra, which provides: 1.
Page 47: Dual Modulation With Pid
6.3 Dual modulation with PID 6.3 Dual modulation with PID It is possible to perform simultaneously with another form of modulation enabled. For example, can be used to compensate for the frequency response of components or the when per- forming wide-band frequency modulation, as shown in Listing 6.1. # enable FM on channel 1 MDN,1,FREQ,ON GAIN,1,FREQ,0x3FFFF...
Page 48: Noise-Eater Implementation
Chapter 6. PID stabilisation 6.4 Noise-eater implementation A common application for controllers is optical noise eating, which technical noise arising from power ﬂuctuations in a laser beam. Figure 6.1 shows a typical conﬁguration, where the intensity of the undiﬀracted (zero-order) beam is stabilised as seen in Figure 6.2. In this conﬁguration, the acts as a high-speed variable optical attenuator, diﬀracting some of the light into the unused ﬁrst-order...
Page 49: Example
6.5 Example measured optical power. If the measured power is too high, the power is increased and more light is diverted into the diﬀracted out- put. This allows ﬂuctuations in intensity to be suppressed, at the expense of reducing the transmitted power slightly (typically 90% transmission is achieved).
Page 50 Chapter 6. PID stabilisation...
Page 51: Digital I/O
7. Digital I/O digital inputs and outputs (0-5 V) are provided on the ARF/XRF through the DE15 connector on the rear panel, and the high-speed bus ( ). The inputs can be used as triggers and the outputs can be controlled manually or using by table mode entries (§8.3). Note: Digital inputs are pulled high, meaning that a disconnected input pin is equivalent to supplying a high to that input.
Page 52 Chapter 7. Digital I/O Signal Type CH1 OFF TTL in CH1 ON TTL in CH1 SEQ(*) TTL in CH1 DOUT TTL out CH2 SEQ(*) TTL in CH2 ON TTL in CH2 OFF TTL in CH2 DOUT TTL out ±2 5 V CH1 AOUT ±2 5 V CH2 AOUT...
Page 53: High-Speed Digital
7.2 High-speed digital CHx-ON Pin 2 (Ch1), Pin 6 (Ch2) to switch ON Driving this pin mode instructs the FPGA both the signal and ampliﬁers (if present). Has no eﬀect if the output is already enabled. For applications that require the ampli- ﬁers to stay powered on, the CHx-OFF pin should be used instead.
Page 54 Chapter 7. Digital I/O Signal Signal Signal 3.3 V 3.3 V 3.3 V Figure 7.2: High-speed digital IO connector (internal). Note that the cable can be inserted upside-down, reversing the pin ordering. Version Driver Bank size Example conﬁguration 74LVT2244 Outputs only 16x outputs Banks of 8 8x inputs, 8x outputs...
Page 55: Xsma Breakout Board
7.3 XSMA breakout board 7.3 XSMA breakout board XSMA breakout board (Figure 7.3) is an optional additional com- ponent that provides connectors for each of the digital lines of both the DE15 connector (§7.1) and the high-speed bus (§7.2). The pins of the high-speed bus have matched track-lengths, to en- sure consistent propagation delay for applications using advanced table mode.
Page 56: Configuration
Chapter 7. Digital I/O 7.4 Conﬁguration EXTIO command is used to control the behaviour of digital I/O. EXTIO,WRITE EXTIO,READ Outputs can be set with , and queried with when set to MANUAL control, or commanded by table mode entries when set to AUTOMATIC control.
Page 57 7.4 Conﬁguration mode either READ WRITE . If , then is either LATCH TOGGLE . If is disabled, it is enabled ﬁrst. R 5+ hardware, the sub-banks can be controlled using a second mode mode command. The ﬁrst argument applies to lines 1–4 of the bank, and the second applies to lines 5–8.
Page 58: Ttl Switching
Chapter 7. Digital I/O 7.5 TTL switching A versatile feature of the ARF/XRF is the ability to switch the in response to an external input such as a tactile switch or a trigger for device synchronisation. Each channels has two inputs on the DE15 connector, labelled...
Page 59: Pulse Generation
7.6 Pulse generation EXTIO,ENABLE,1,OFF Enable the CHx-OFF behaviour, as previously conﬁgured by the EXTIO,MODE command. EXTIO,DISABLE,1,OFF Disable the CHx-OFF input, regular operation using the commands. Please note that this setting is not stored persistently and needs to be explicitly re-enabled after powering on the device where desired. Furthermore, in devices the input also serves dual-...
Page 60 Chapter 7. Digital I/O Method Transition Time switch 25 ns switch 30 ns AM (fast) 500 ns < 3 us AM (slow) DE15 2 ms DE15 -OFF 40 ns Table 7.2: Typical on/oﬀ time delays for switching hardware components, and for diﬀerent methods of pulse generation (debouncer disabled). The time given for ampliﬁer transitions includes time for the output to stabilise, which may vary between hardware revisions.
Page 61: Counters
7.7 Counters Figure 7.5: Example of pulse generation using the CHx-OFF input. Red is signal; blue is the signal. 7.7 Counters Fast digital counters can be accessed for each digital input pin. devices can use these counters in advanced table mode (§9.4); devices can only use them manually in scripts.
Page 62: Examples
Chapter 7. Digital I/O H[IGH] Count while input is HIGH , enables counter L[OW] Count while input is , enables counter R[ISING] Count rising edges, enables counter F[ALLING] Count falling edges, enables counter B[OTH] Count both rising and falling edges, enables counter The following -mode example sets up a rising edge counter on and counts for approximately 100 ms.
Page 63 7.8 Examples EXTIO,WRITE,1,HS7,ON Sets port 7 of HSB1 to TTL HIGH EXTIO,WRITE,1,HSB,0x7 Simultaneously writes all pins in HSB1 . Sets pins 0-2 HIGH and pins 3-7 EXTIO,MODE,2,HSB,READ Sets the entire second high-speed bank into read mode (only available in R 3+ models) EXTIO,READ,2,HSB Simultaneously read all 8-inputs of the second...
Page 64 Chapter 7. Digital I/O...
Page 65: Simple Table Mode
8. Simple table mode Table mode performs sequential execution of up to 8191 instruc- tions with precise timing. This enables generation of complicated pulse sequences, custom envelope shapes, and automated control of experiment sequences through digital I/O. There are two versions of table mode: simple table mode ( mode) serial interface, and advanced table mode which utilises the...
Page 66: Defining Table Entries
Chapter 8. Simple table mode TABLE,START trigger on the input or using the command. The phase-accumulator of the is then reset and the table exe- cutes autonomously under FPGA control. This provides a very high degree of reproducibility in terms of both timing of instructions and output of the generators, as the phase accumulator is reset...
Page 67 8.2 Deﬁning table entries TABLE,ENTRY TABLE,ENTRY,ch,num,[freq,pow,phas,dur,flags] Conﬁgure the speciﬁed table entry. If only are given, the current entry of the table is returned. The channel to edit (1 or 2) The entry to edit (1 to 8191) freq Frequency to output during this step Output power during this step phas Phase of the...
Page 68 Chapter 8. Simple table mode TABLE,INSERT TABLE,INSERT,ch,num,freq,pow,phas,dur,flags Insert the speciﬁed entry into the table at the speciﬁed index, and shift all other entries down. TABLE,DELETE TABLE,DELETE,ch,num Remove only the speciﬁed entry from the table. TABLE,CLEAR TABLE,CLEAR,ch Deletes the entire table from memory and resets any state variables. TABLE,ENTRY Listing 8.1 shows basic operation of table mode using the command to deﬁne the instructions.
Page 69: Digital I/O
8.3 Digital I/O Figure 8.1: Demonstration of Listing 8.1 on an ARF021 8.3 Digital I/O Each entry in the table can control a single digital I/O pin (§8.3.1), or write multiple pins simultaneously (§8.3.2). However, pins must EXTIO be correctly conﬁgured using the...
Page 70 Chapter 8. Simple table mode as this channel (A for , B for A0-A7 The speciﬁed pin of high-speed bank A (irrespective of channel) B0-B7 The speciﬁed pin of high-speed bank B (irrespective of channel) Both channels are capable of accessing the same I/O pins using the second notation.
Page 71 8.3 Digital I/O TABLE,ENTRY,1,2,100MHz,0x600,0,2,IO1H # 2us later, set pin 1 low TABLE,ENTRY,1,3,100MHz,0x1000,0,2,IO1L TABLE,ENTRY,1,4,100MHz,0x1400,0,2 # create 500ns pulse TABLE,ENTRY,1,5,100MHz,0x2000,0,2,IO1P TABLE,ENTRY,1,6,100MHz,0x200,0,2 # toggle pin 1 (from low to high) TABLE,ENTRY,1,7,100MHz,0x600,0,2,IO1T TABLE,ENTRY,1,8,100MHz,0x1000,0,2 # toggle pin 1 again (i.e. from high to low) TABLE,ENTRY,1,9,100MHz,0x1400,0,2,IO1T TABLE,ENTRY,1,10,100MHz,0x2000,0,2 TABLE,ENTRIES,1,10 Listing 8.2: Simple example showing digital output in table mode.
Page 72 Chapter 8. Simple table mode 8.3.2 Simultaneous digital output As of ﬁrmware v1.3.0, multiple digital outputs can be set simultane- IOSET IOMASK ously in a single table instruction using the ﬂags. Both instructions take a 16-bit number, where each bit corresponds IOMASK to a pin of the high-speed output banks.
Page 73: Loops And Triggers
8.4 Loops and triggers IOMASK0x00FF For reference, the ﬂag will only write to bank A, and IOMASK0xFF00 will only write to bank B. It is recommended to encode values in hexadecimal in this way to improve readability. Note: Multiple digital output mode cannot be used in combination with LOOP TRIG 8.4 Loops and triggers...
Page 74 Chapter 8. Simple table mode at the loop instruction H[IGH] Terminate loop on logic level HIGH at the loop instruction L[OW] Terminate loop on logic level Terminate loop after falling edge occurs F[ALLING] Terminate loop after rising edge occurs R[ISING] Note: When using the inputs as a trigger in table mode, it is strongly recom- DEBOUNCE...
Page 75 8.4 Loops and triggers TABLE,LOOP,1,3,1,4 TABLE,APPEND,1,100MHz,-30dBm,0,1us,OFF TABLE,APPEND,1,100MHz,-30dBm,0,1us,OFF TABLE,APPEND,1,100MHz,-30dBm,0,1us,OFF Listing 8.3: Demonstration of a simple loop Figure 8.3: Demonstration of a simple loop. LOOP An alternate way of specifying the instruction in the above TABLE,LOOP,1,-1,-2,4 example is , since the loop should activate after the most recently added entry (source -1), and the destination (entry 1) is 2 instructions earlier.
Page 76 Chapter 8. Simple table mode Similarly to the general loop, the trigger behaviour is to repeat the current instruction until a trigger is received. If the trigger condition is met during the instruction period, the duration of the TRIG current instruction is completed ﬁrst. Hence the duration of a instruction should be as small as possible to ensure rapid response.
Page 77: Upload And Download
8.5 Upload and download TABLE,ARM Once a table is armed with the command it will automat- ically begin executing upon a falling external trigger on the DE15 input. Starting the table execution from an external trigger there- TRIG fore does not require the ﬂag on the ﬁrst table entry.
Page 78: Re-Arm And Restart
Chapter 8. Simple table mode MODE,1,TSB TABLE,CLEAR,1 TABLE,ENTRIES,1,4 TABLE,ENTRY,1,1,100MHz,-5dBm,0deg,10us TABLE,ENTRY,1,2,150MHz,0dBm,90deg,2us,IODH TABLE,ENTRY,1,3,80MHz,5dBm,0deg,1us,TRIG TABLE,ENTRY,1,4,100MHz,0dBm,0deg,5us Listing 8.6: Script equivalent to Listing 8.5. 8.6 Re-arm and restart FPGA can be instructed to automatically re-arm the table after TABLE,REARM a successful execution using the command. This auto- matically prepares the table for execution from either hardware or software trigger once execution has ﬁnished.
Page 79: Linear Ramps
8.7 Linear ramps # ... Instructions that deﬁne the CH1 table ... # add a LOOP from the most recent instruction ( 1) back to the start (1) TABLE,LOOP,1,-1,1,4095 # last three instructions cannot be a loop add dummy instructions TABLE,APPEND,1,100MHz,-30dBm,0,1us TABLE,APPEND,1,100MHz,-30dBm,0,1us TABLE,APPEND,1,100MHz,-30dBm,0,1us...
Page 80 Chapter 8. Simple table mode MODE,1,TSB # clear the table TABLE,CLEAR,1 # deﬁne initial conditions (i.e. freq and phase) TABLE,APPEND,1,80MHz,-30dBm,0deg,1us # ramp power from 30dBm to 0dBm in 100us, then down again TABLE,RAMP,1,POW,-30,0,1us,100 TABLE,RAMP,1,POW,0,-30,1us,100 # should now have 201 entries TABLE,ENTRIES,1 # arm the table TABLE,ARM,1...
Page 81: Synchronous Table Execution
8.8 Synchronous table execution MODE,1,TSB TABLE,CLEAR,1 # set initial conditions TABLE,APPEND,1,80MHz,0dBm,0,1us # deﬁne ﬁrst ramp TABLE,RAMP,1,FREQ,70,80,1m,1000 # append a pause TABLE,APPEND,1,80,-5dbm,0,1s # append second and third ramps TABLE,RAMP,1,FREQ,80,75,5m,200 TABLE,RAMP,1,FREQ,75,85,2m,500 Listing 8.9: Example demonstrating use of TABLE,RAMP to create multiple frequency ramps. Figure 8.6: Frequency ramps achieved by chaining together RAMPFREQ commands in...
Page 82 Chapter 8. Simple table mode Figure 8.7: Example showing the two outputs when executing the same table synchronously on both channels. TABLE,SYNC,1 This feature is activated by issuing the command . This conﬁgures as the “master” and as the “slave”, such that the CH2 DDS derives its clock from the CH1 DDS...
Page 83: Advanced Table Mode (Xrf)
9. Advanced table mode (XRF) has access to an advanced table mode with increased func- tionality, ﬂexibility and signiﬁcantly faster execution than normal ) table mode. Due to the added complexity, it is strongly recom- mended that users be familiar with simple table mode before reading this chapter.
Page 84: Defining Table Entries
Chapter 9. Advanced table mode (XRF) It should also be noted that the while the outputs can be syn- chronised, the rf components following the introduce a small frequency-dependent propagation delay. However, this delay is ﬁxed for a given frequency, and can be calibrated in applications where it is important.
Page 85 9.2 Deﬁning table entries The listing below demonstrates how to set up advanced table mode to control the envelope (amplitude) of the signal, # enter fast table mode MODE,1,TPA # clear any table entries or settings TABLE,CLEAR,1 # set amplitude (power) as the parallel parameter TABLE,XPARAM,1,POW # deﬁne a table TABLE,APPEND,1,POW,5dbm,16ns...
Page 86 Chapter 9. Advanced table mode (XRF) It is anticipated that many applications will only seek to control a single parameter, in which case only the parallel interface need be used. However, a second command format is provided to simultane- ously set all three parameters using the serial interface. TABLE,ENTRY TABLE,ENTRY,ch,num,freq,pow,phase,duration,flags Deﬁnes a serial (...
Page 87 9.2 Deﬁning table entries # some other instructions while the SIF loads TABLE,APPEND,1,POW,-5dbm,320ns TABLE,APPEND,1,POW,-10dbm,320ns TABLE,APPEND,1,POW,-5dbm,320ns # trigger the serial instruction TABLE,APPEND,1,POW,5dbm,200ns,UPD # another parallel instruction at new frequency TABLE,APPEND,1,POW,-5dbm,100ns # ﬁnal instruction to power down TABLE,APPEND,1,POW,0x0,0x1 Listing 9.3: Demonstration of parallel instructions during a SIF load Figure 9.2: Output generated by Listing 9.3 Note: The value corresponding to the parallel parameter is ignored when loading a serial update and must be set separately.
Page 88: Initial And Final States
Chapter 9. Advanced table mode (XRF) 9.3 Initial and ﬁnal states TABLE,ARM As in simple table mode, when the command is used to ready the table for execution, the output is enabled and ampliﬁers switched on (if present). The state of the after arming is therefore the same as the last table instruction that was run.
Page 89: Counters
9.4 Counters instruction will remain unless subsequently overwritten by one of these commands. It is therefore strongly recommended to specify the initial and ﬁnal states. 9.4 Counters devices are capable of controlling the digital input counters in advanced table mode, and using the counters as a loop condition. This assists in experiment automation, whereby the execution can be paused until a critical count is received.
Page 90: Loops And Triggers
Chapter 9. Advanced table mode (XRF) The example below shows how to conﬁgure a counter, control it with table ﬂags, and use it as a loop condition. # conﬁgure the counter EXTIO,MODE,1,HSB,READ # set bank A into read mode EXTIO,COUNTER,1,HS1,FALLING # set pin A1 to count falling edges # create the table MODE,1,TPA...
Page 91: Linear Ramps Using Extrapolation
9.6 Linear ramps using extrapolation 9.6 Linear ramps using extrapolation One of the powerful features provided in advanced table mode is the ability to specify linear ramps in parallel mode, which reduces the number of instructions necessary to produce smooth piecewise- linear ramps.
Page 92 Chapter 9. Advanced table mode (XRF) Listing 9.6 demonstrates how to linearly ramp the power in 100 steps using a single instruction instead of 100 individual instructions REPn by using the notation. The result is shown in Figure 9.3. Listing 9.7 demonstrates an equivalent formulation based on the TABLE,RAMP command, which provides the convenience of specifying the power in real units (dBm) instead of hexadecimal increments.
Page 93: Frequency Gain
9.7 Frequency gain Figure 9.3: Output generated by Listing 9.6. 9.7 Frequency gain The fast (parallel) interface to the is 16-bit, which is suﬃcient to fully deﬁne the amplitude (14-bits) and phase (16-bits) but not frequency (32-bits). This is an inherent restriction of the , so in order to specify frequency on the parallel interface, a “frequency gain”...
Page 94 Chapter 9. Advanced table mode (XRF) This has the eﬀect of restricting the smallest and largest changes that can be made in parallel frequency mode through the associ- ated frequency discretisation (step size) and value range. If large changes to frequency are required, high gain should be used. If high resolution is required, small gain should be used.
Page 95: Other Instruction Parameters
9.8 Other instruction parameters For example, to vary the frequency between 70 MHz and 80 MHz with maximum dynamic range, the frequency should be set to 75 MHz FREQ using the command, and the frequency gain set to 10. However, to vary between 65 MHz and 85 MHz, the gain must be increased to 11.
Page 96: Additional Examples
Chapter 9. Advanced table mode (XRF) 9.9 Additional examples 9.9.1 Gaussian envelope The following example demonstrates creation of a short (300 ns) Gaussian pulse by specifying the output power at the maximum up- date rate (instruction duration 0 1 = 16 ns). The resulting output waveform is shown in Figure 9.5.
Page 97 9.9 Additional examples Figure 9.5: Example of a short Gaussian pulse. 9.9.2 Back-to-back pulses with diﬀerent frequency This example demonstrates how to generate two back-to-back 1 s pulses with diﬀerent frequencies by loading the second frequency during the ﬁrst pulse. The EXTRAPOLATE feature is used to smooth the envelope, and the...
Page 98 Chapter 9. Advanced table mode (XRF) TABLE,APPEND,1,POW,0x0264,0x1,REP3 TABLE,APPEND,1,POW,0x0222,0x1,REP3 TABLE,APPEND,1,POW,0x017b,0x1,REP3 TABLE,APPEND,1,POW,0x0088,0x1,REP3 TABLE,APPEND,1,POW,-0x088,0x1,REP3 TABLE,APPEND,1,POW,-0x17b,0x1,REP3 TABLE,APPEND,1,POW,-0x222,0x1,REP3 TABLE,APPEND,1,POW,-0x264,0x1,REP3 TABLE,APPEND,1,POW,-0x244,0x1,REP3 TABLE,APPEND,1,POW,-0x1db,0x1,REP3 TABLE,APPEND,1,POW,-0x153,0x1,REP3 TABLE,APPEND,1,POW,-0x0d1,0x1,REP3 TABLE,APPEND,1,POW,-0x06a,0x1,REP3 TABLE,APPEND,1,POW,-0x01f,0x1,REP3 # trigger the frequency change TABLE,APPEND,1,HOLD,0x1,UPD # loop back to create second pulse TABLE,LOOP,1,-1,4,1 TABLE,APPEND,1,POW,0x0,0x1 Listing 9.9: Back-to-back shaped pulses with diﬀerent frequencies Figure 9.6: Two 1 s Gaussian pulses generated in advanced table mode with amplitude on the parallel bus.
Page 99 9.9 Additional examples 9.9.3 Parallel frequency mode The following example demonstrates control of the frequency with the parallel interface. # set up table mode MODE,1,TPA TABLE,CLEAR,1 # use HSB for triggering EXTIO,CTRL,1,HSB,AUTO # change to FREQ mode and set the FM gain TABLE,XPARAM,1,FREQ,15 # step through a number of frequencies TABLE,APPEND,1,FREQ,20,0x5,IOA1H...
Page 100 Chapter 9. Advanced table mode (XRF)
Page 101: Specifications
A. Speciﬁcations Speciﬁcation Parameter RF characteristics +36 dBm/+16 dBm (421/021 models) Max output power 14-bit resolution Amplitude control 20 to 400 MHz Frequency 32-bit resolution; 0.232831 Hz steps Frequency control ◦ ±1 ppm (0 to 50 Frequency stability 0 to 2π (16-bit resolution) Phase <...
Page 102 Appendix A. Speciﬁcations Digital input/output (per channel) hardwired, positive logic only RF on/oﬀ input to continue table execution Trigger input output on DE15 connector Shutter output 16 x shared High-speed I/O 2.2 V TTL input high 0.6 V TTL input low 7.0 V Absolute max in -0.5 V...
Page 103: Firmware Upgrades
B. Firmware upgrades From time to time, MOGL abs will release updates to the ARF/XRF ﬁrmware, which enable new functionality or address issues in the version which shipped with your device. This section contains in- structions on how to apply ﬁrmware updates to your device. The device ﬁrmware consists of several components.
Page 104: Factory Reset
Appendix B. Firmware upgrades B.2 Factory reset If a ﬁrmware upgrade fails and the device subsequently cannot boot, a factory reset (rebooting with set to ) must be applied. The DIP4 device will then attempt to restore the conﬁguration it was shipped with to restore operation.
Page 105 B.3 Upgrade via mogrffw Figure B.1: The mogrffw ﬁrmware update application connected to a unit, showing the serial number (1), model (2) and current ﬁrmware versions (3). Note that some values may be unavailable if the device is in “ﬁrmware up- date mode”.
Page 106 Appendix B. Firmware upgrades Figure B.2: The mogrffw ﬁrmware update application. The versions run- ning on the device are compared against the selected package, in this instance showing that an update is available for the UC (yellow) and the other components are up-to-date (green). The upload process proceeds through four stages: 1.
Page 107: Upgrade Via Web Interface
4. Use a web browser and connect to the speciﬁed IP address. 5. At the prompt, enter your user ID and password. These are user-conﬁgurable but by default are moglabs UserID: agilerf Password: 6. Select Browse and then select the microcontroller ﬁrmware ﬁle.
Page 108: Upgrading An Arf To An Xrf
Appendix B. Firmware upgrades B.5 Upgrading an to an It is possible to ﬁeld-upgrade an into an to gain access to advanced table mode, using the upgrade tool provided as part of the mogrf distribution (Figure B.3). It may be necessary to install a new version of mogrf to access this program.
Page 109: Command Language
Please note: The command language is being continuously updated across ﬁrmware releases to improve functionality and add features. When upgrading ﬁrmware, please refer to the most recent version of the manual available at http://www.moglabs.com C.1 Arguments Most commands require a channel number “...
Page 110: General Functions
Appendix C. Command language If required, values corresponding to internal representation can be speciﬁed directly using hexadecimal format with a “0x” preﬁx. This is potentially useful for stepping through the discrete values that AD9910 is capable of generating. C.2 General functions REBOOT Initiate microcontroller reset, causing unit to reboot.
Page 111: Primary Rf Control
C.4 Primary control Turn oﬀ/on the signal only. Turn oﬀ/on the high-power ampliﬁer only. Note that the ampliﬁers take 2 s to completely power on. Turn oﬀ/on both the signal and high-power ampliﬁer (default). STATUS STATUS[,ch] Reports the current operational status of the speciﬁed channel, de- scribing whether the signal and ampliﬁers are switched on.
Page 112 Appendix C. Command language The following examples will generate approximately 250 mW output power on ARF421 devices: POW,1,0x1000 POW,1,250 mW POW,1,24 dBm AUTOPOW AUTOPOW,ch[,enable][,power] mode only. and never ARF/XRF devices are able to com- pensate for the frequency dependency of the signal path using power meters that monitor the actual output power and feed back to amplitude control.
Page 113: Modulation
C.5 Modulation DEBOUNCE DEBOUNCE,ch[,off/on] digital DE15 control inputs can be debounced to allow op- eration with noisy signals, such as from a push-button or toggle DEBOUNCE switch. The command enables or disables the debounce ﬁlter for the selected channel (default: SINCFILTER SINC,ch[,onoff] Activate or deactivate the internal sinc ﬁlter of the...
Page 114 Appendix C. Command language gain Optionally specify gain for this modulation type as an integer (does GAIN not accept units); equivalent to subsequently using the com- mand. GAIN GAIN,ch,mdntype[,gain] Sets the modulation gain for the speciﬁed modulation type on the gain given channel.
Page 115: Digital Ramp Generator
C.6 Digital ramp generator C.6 Digital ramp generator AD9910 contains a digital ramp generator ( ) for linear param- eter sweeps. This behaviour is controlled directly in mode using registers (§C.13) in consultation with the AD9910 datasheet, or using the commands below. RAMPBIT RAMPBIT,ch[,value] Enables or disables ramp functionality.
Page 116: Monitor Outputs
Appendix C. Command language FREQ immediately after programming. The command cannot be used RAMPFREQ when has been activated. RAMPFREQ Note that issuing a second command will stop any previ- ously conﬁgured ramp and replace it. However, ramps can be joined together in table mode.
Page 117: Clock Reference
C.8 Clock reference FHLRAMP Fast linear ramp (2Vpp, 12.5kHz), high-to-low (falling) SLHRAMP Slow linear ramp (2Vpp, 5.7Hz), low-to-high (rising) SHLRAMP Slow linear ramp (2Vpp, 5.7Hz), high-to-low (falling) FWD1, FWD2 Monitor for the transmitted (forward) output power REV1, REV2 Monitor for the reﬂected (reverse) power PID1, PID2 PID,MONITOR Monitor for the PID loop, see also the...
Page 118 Appendix C. Command language ppln If the clock source is 1 GHz, then must be set to zero. This disables the and improves the phase-noise of the output. ppln Except for this special case, valid ranges for are [12,127], which means the reference must be the range 7.87 MHz to 83.3 MHz.
Page 119: Table Mode
C.9 Table mode C.9 Table mode Table mode gives access to the powerful sequencing functionality of devices (chapter 8). devices also have access to advanced table mode (chapter 9), which is controlled using the same TABLE commands. TABLE,ARM,ch for execution, typically taking ∼ 100 s. Loads the table into the FPGA The table then begins execution upon receiving a software trigger...
Page 120 Appendix C. Command language RESTART TABLE,RESTART,ch[,on/off] Enables/disables an automatic software-controlled restart of the ta- REARM ble upon completion. Automatically enables . Table will then begin executing upon a software or hardware trigger. STATUS TABLE,STATUS,ch Reports the current execution status of the table. ENTRIES TABLE,ENTRIES,ch[,num] Deﬁnes the last table entry number for the given channel.
Page 121 C.9 Table mode start stop count duration from steps, each lasting . In simple count table mode this generates table entries, whereas in advanced table mode it generates up to three. SAVE TABLE,SAVE,ch,slot slot Save the current table in a FLASH memory slot, where is a num-...
Page 122: Pid Feedback
Appendix C. Command language every execution. However, this requires switching oﬀ for a few mi- croseconds while the is reset, which is undesirable for some NORESET applications. Using will ensure the output stays on. XPARAM TABLE,XPARAM[,mode][,gain] mode only ( ). Set the parameter to be modiﬁed on the paral- mode FREQ lel bus in advanced table mode.
Page 123 C.10 PID feedback If speciﬁed, the voltage must be between -1 and +1 V. Note that the lock may become unstable close to these limits due to clipping of the error signal. AVERAGE PID,AVERAGE,ch[,on/off] Enables/disables averaging of the input control signal. The digitis- ers operate at much higher rates than the sampling rate.
Page 124: External Io Functions
Appendix C. Command language C.11 External IO functions Controls the behaviour of the digital lines on the DE15 and 30-pin high-speed connectors as described in chapter 7. Note the high- speed banks on devices are output-only. EXTIO,fn,ch,pin,[parameters] Command structure: ENABLE Enables the main or default function of the pin.
Page 125 C.11 External IO functions mode , then must be one of READ Conﬁgure the 8 pins of the bank for input ( R 3+ only). WRITE Conﬁgure the 8 pins of the bank for output. This command does not apply to any other pins. CONTROL Sets or returns the current control mechanism for the speciﬁed pin.
Page 126: Configuration Settings
Appendix C. Command language C.12 Conﬁguration settings SET, GET Set and report EEPROM conﬁguration values. Each command described below has a corresponding command to report the relevant parameter. ipaddr SET,ipaddr,"xxx.xxx.xxx.xxx" address based on decimal dotted-quad string (for example ”10.1.1.180”). Note that the double-quotes are part of the syntax and must be included to delimit the address string.
Page 127: Direct Dds Control
C.13 Direct DDS control C.13 Direct DDS control For direct control the the chips, mode is provided. This allows direct access to the registers, but only a limited subset of commands are unavailable. WARNING: Using these commands bypasses all safeguards and can result in unde- ﬁned behaviour or damage to connected devices.
Page 128 Appendix C. Command language PHAS Phase oﬀset word (16-bit) AMPL Amplitude scale factor (32-bit) SYNC Multichip sync (32-bit) RLIM Digital ramp limit (64-bit) RSTP Digital ramp step size (64-bit) RRTE Digital ramp rate (32-bit) STP[0-7] Single tone proﬁle 0-7 (64-bit) RAMW RAM word register (32-bit) DINIT...
Page 129: Code Examples
D.1 python Communication is handled by a “device” class, which provides con- venience functions for sending commands and queries. # ARF python example, (c) MOGLabs 2016 from mogdevice import MOGDevice # connect to the device dev = MOGDevice(’10.1.1.23’) # print some information print ’Device info:’, dev.ask(’info’)
Page 130 Appendix D. Code examples # ARF Gaussian pulse example, (c) MOGLabs 2016 from mogdevice import MOGDevice import numpy as np # connect to the device dev = MOGDevice(’10.1.1.45’) print ’Device info:’, dev.ask(’info’) # construct the pulse N = 200 X = np.linspace(-2,2,N) Y = 30*(np.exp(-X**2)-1)
Page 131: Matlab
ARF/XRF how to create a simple table that produces a pulse with a Gaussian envelope. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % ARF MATLAB example, (c) MOGLabs 2017 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % create a device instance dev = mogdevice(); % example: connecting by ethernet dev.connect(’10.1.1.31’);...
Page 132: Labview
Appendix D. Code examples D.3 LabVIEW The LabVIEW drivers provided make use of NI-VISA to provide a uniﬁed interface over both ethernet and . They perform automatic error checking, and are compatible with LabVIEW-2009 and later editions. Figure D.2: Example LabVIEW program that connects to an ARF unit, and performs a number of queries When using these drivers, it is strongly recommended that the au- tomatic session close option be enabled, to prevent communications...
Page 134 2015 – 2019 MOG Laboratories Pty Ltd 49 University St, Carlton VIC 3053, Australia Product speciﬁcations and descriptions in this doc- Tel: +61 3 9939 0677 info@moglabs.com ument are subject to change without notice.

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Arf421 Xrf021 Xrf421

MOGlabs ARF021 Manual

Safety Precautions

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1 Introduction

2 Connections and Controls

3 Communications

4 MOGRF Host Software

5 External Modulation

6 PID Stabilisation

7 Digital I/O

8 Simple Table Mode

9 Advanced Table Mode (XRF)

Specifications

Firmware Upgrades

Command Language

Code Examples

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