Clock Reference - MOGlabs ARF021 Manual

C.8 Clock reference
FHLRAMP
SLHRAMP
SHLRAMP
FWD1, FWD2
REV1, REV2
PID1, PID2
C.8 Clock reference
CLKSRC
Fast linear ramp (2Vpp, 12.5kHz), high-to-low (falling)
Slow linear ramp (2Vpp, 5.7Hz), low-to-high (rising)
Slow linear ramp (2Vpp, 5.7Hz), high-to-low (falling)
Monitor for the transmitted (forward) output power
Monitor for the reflected (reverse) power
Monitor for the PID loop, see also the
The devices operate from an internal clock (
DDS
quency = 1 GHz, which is derived either from the oven-
SYSCLK
stabilised crystal oscillator at 20 MHz ("internal" mode) or provided
via the input labelled
SMA
Each DDS multiplies this reference clock and stabilises with an in-
ternal phase-locked loop (
the 20–400 MHz range. This provides flexibility at the expense of a
small increase in phase noise. In applications where minimal phase
noise is critical, a stable 1 GHz reference should be provided that
directly clocks the DDS
CLKSRC[,source][,ppln]
Query or set the current clock source.
the internal 20 MHz oscillator, or
to the CLK IN connector on the back-panel, compatible with a number
of standard reference frequencies (such as a 10 MHz
When using external reference, the
must be provided. This is 1 GHz divided by the external clock fre-
quency, rounded to the nearest integer. Wherever possible, the ex-
ternal clock frequency should be chosen to ensure no remainder to
prevent accumulation of timing errors.
("external" mode).
CLK IN
PLL ) to generate output frequencies across
without the need for frequency multiplication.
source
EXT
to use the reference provided
ppln
PID,MONITOR
command.
) at fre-
SYSCLK
INT
is either
GPS clock).
"clock multiplier" value
107
to use